xref: /linux/Documentation/devicetree/bindings/clock/qcom,sar2130p-gcc.yaml (revision 7f4f3b14e8079ecde096bd734af10e30d40c27b7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sar2130p-gcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on sar2130p
8
9maintainers:
10  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11
12description: |
13  Qualcomm global clock control module provides the clocks, resets and
14  power domains on sar2130p.
15
16  See also: include/dt-bindings/clock/qcom,sar2130p-gcc.h
17
18properties:
19  compatible:
20    const: qcom,sar2130p-gcc
21
22  clocks:
23    items:
24      - description: XO reference clock
25      - description: Sleep clock
26      - description: PCIe 0 pipe clock
27      - description: PCIe 1 pipe clock
28      - description: Primary USB3 PHY wrapper pipe clock
29
30  protected-clocks:
31    maxItems: 240
32
33  power-domains:
34    maxItems: 1
35
36required:
37  - compatible
38  - clocks
39  - '#power-domain-cells'
40
41allOf:
42  - $ref: qcom,gcc.yaml#
43
44unevaluatedProperties: false
45
46examples:
47  - |
48    #include <dt-bindings/clock/qcom,rpmh.h>
49    #include <dt-bindings/power/qcom,rpmhpd.h>
50
51    gcc: clock-controller@100000 {
52        compatible = "qcom,sar2130p-gcc";
53        reg = <0x100000 0x1f4200>;
54        clocks = <&rpmhcc RPMH_CXO_CLK>,
55                 <&sleep_clk>,
56                 <&pcie_0_pipe_clk>,
57                 <&pcie_1_pipe_clk>,
58                 <&usb_0_ssphy>;
59        power-domains = <&rpmhpd RPMHPD_CX>;
60
61        #clock-cells = <1>;
62        #reset-cells = <1>;
63        #power-domain-cells = <1>;
64    };
65...
66