xref: /linux/Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml (revision a3a02a52bcfcbcc4a637d4b68bf1bc391c9fad02) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sa8775p-gcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on sa8775p
8
9maintainers:
10  - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
11
12description: |
13  Qualcomm global clock control module provides the clocks, resets and
14  power domains on sa8775p.
15
16  See also:: include/dt-bindings/clock/qcom,sa8775p-gcc.h
17
18properties:
19  compatible:
20    const: qcom,sa8775p-gcc
21
22  clocks:
23    items:
24      - description: XO reference clock
25      - description: Sleep clock
26      - description: UFS memory first RX symbol clock
27      - description: UFS memory second RX symbol clock
28      - description: UFS memory first TX symbol clock
29      - description: UFS card first RX symbol clock
30      - description: UFS card second RX symbol clock
31      - description: UFS card first TX symbol clock
32      - description: Primary USB3 PHY wrapper pipe clock
33      - description: Secondary USB3 PHY wrapper pipe clock
34      - description: PCIe 0 pipe clock
35      - description: PCIe 1 pipe clock
36      - description: PCIe PHY clock
37      - description: First EMAC controller reference clock
38      - description: Second EMAC controller reference clock
39
40  protected-clocks:
41    maxItems: 240
42
43  power-domains:
44    maxItems: 1
45
46required:
47  - compatible
48  - clocks
49  - '#power-domain-cells'
50
51allOf:
52  - $ref: qcom,gcc.yaml#
53
54unevaluatedProperties: false
55
56examples:
57  - |
58    #include <dt-bindings/clock/qcom,rpmh.h>
59    #include <dt-bindings/power/qcom-rpmpd.h>
60
61    gcc: clock-controller@100000 {
62        compatible = "qcom,sa8775p-gcc";
63        reg = <0x100000 0xc7018>;
64        clocks = <&rpmhcc RPMH_CXO_CLK>,
65                 <&sleep_clk>,
66                 <&ufs_phy_rx_symbol_0_clk>,
67                 <&ufs_phy_rx_symbol_1_clk>,
68                 <&ufs_phy_tx_symbol_0_clk>,
69                 <&ufs_card_rx_symbol_0_clk>,
70                 <&ufs_card_rx_symbol_1_clk>,
71                 <&ufs_card_tx_symbol_0_clk>,
72                 <&usb_0_ssphy>,
73                 <&usb_1_ssphy>,
74                 <&pcie_0_pipe_clk>,
75                 <&pcie_1_pipe_clk>,
76                 <&pcie_phy_pipe_clk>,
77                 <&rxc0_ref_clk>,
78                 <&rxc1_ref_clk>;
79        power-domains = <&rpmhpd SA8775P_CX>;
80
81        #clock-cells = <1>;
82        #reset-cells = <1>;
83        #power-domain-cells = <1>;
84    };
85...
86