1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/qcom,sa8775p-dispcc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display Clock & Reset Controller on SA8775P 8 9maintainers: 10 - Taniya Das <quic_tdas@quicinc.com> 11 12description: | 13 Qualcomm display clock control module provides the clocks, resets and power 14 domains on SA8775P. 15 16 See also: include/dt-bindings/clock/qcom,sa8775p-dispcc.h 17 18properties: 19 compatible: 20 enum: 21 - qcom,sa8775p-dispcc0 22 - qcom,sa8775p-dispcc1 23 24 clocks: 25 items: 26 - description: GCC AHB clock source 27 - description: Board XO source 28 - description: Board XO_AO source 29 - description: Sleep clock source 30 - description: Link clock from DP0 PHY 31 - description: VCO DIV clock from DP0 PHY 32 - description: Link clock from DP1 PHY 33 - description: VCO DIV clock from DP1 PHY 34 - description: Byte clock from DSI0 PHY 35 - description: Pixel clock from DSI0 PHY 36 - description: Byte clock from DSI1 PHY 37 - description: Pixel clock from DSI1 PHY 38 39 power-domains: 40 maxItems: 1 41 description: MMCX power domain 42 43required: 44 - compatible 45 - clocks 46 - power-domains 47 - '#power-domain-cells' 48 49allOf: 50 - $ref: qcom,gcc.yaml# 51 52unevaluatedProperties: false 53 54examples: 55 - | 56 #include <dt-bindings/clock/qcom,rpmh.h> 57 #include <dt-bindings/power/qcom-rpmpd.h> 58 #include <dt-bindings/clock/qcom,sa8775p-gcc.h> 59 clock-controller@af00000 { 60 compatible = "qcom,sa8775p-dispcc0"; 61 reg = <0x0af00000 0x20000>; 62 clocks = <&gcc GCC_DISP_AHB_CLK>, 63 <&rpmhcc RPMH_CXO_CLK>, 64 <&rpmhcc RPMH_CXO_CLK_A>, 65 <&sleep_clk>, 66 <&dp_phy0 0>, 67 <&dp_phy0 1>, 68 <&dp_phy1 2>, 69 <&dp_phy1 3>, 70 <&dsi_phy0 0>, 71 <&dsi_phy0 1>, 72 <&dsi_phy1 2>, 73 <&dsi_phy1 3>; 74 power-domains = <&rpmhpd SA8775P_MMCX>; 75 #clock-cells = <1>; 76 #reset-cells = <1>; 77 #power-domain-cells = <1>; 78 }; 79... 80