xref: /linux/Documentation/devicetree/bindings/clock/qcom,qcs615-gpucc.yaml (revision 8d2b0853add1d7534dc0794e3c8e0b9e8c4ec640)
1*3590dfbdSTaniya Das# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*3590dfbdSTaniya Das%YAML 1.2
3*3590dfbdSTaniya Das---
4*3590dfbdSTaniya Das$id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
5*3590dfbdSTaniya Das$schema: http://devicetree.org/meta-schemas/core.yaml#
6*3590dfbdSTaniya Das
7*3590dfbdSTaniya Dastitle: Qualcomm Graphics Clock & Reset Controller on QCS615
8*3590dfbdSTaniya Das
9*3590dfbdSTaniya Dasmaintainers:
10*3590dfbdSTaniya Das  - Taniya Das <quic_tdas@quicinc.com>
11*3590dfbdSTaniya Das
12*3590dfbdSTaniya Dasdescription: |
13*3590dfbdSTaniya Das  Qualcomm graphics clock control module provides clocks, resets and power
14*3590dfbdSTaniya Das  domains on QCS615 Qualcomm SoCs.
15*3590dfbdSTaniya Das
16*3590dfbdSTaniya Das  See also: include/dt-bindings/clock/qcom,qcs615-gpucc.h
17*3590dfbdSTaniya Das
18*3590dfbdSTaniya Dasproperties:
19*3590dfbdSTaniya Das  compatible:
20*3590dfbdSTaniya Das    const: qcom,qcs615-gpucc
21*3590dfbdSTaniya Das
22*3590dfbdSTaniya Das  clocks:
23*3590dfbdSTaniya Das    items:
24*3590dfbdSTaniya Das      - description: Board XO source
25*3590dfbdSTaniya Das      - description: GPLL0 main branch source
26*3590dfbdSTaniya Das      - description: GPLL0 GPUCC div branch source
27*3590dfbdSTaniya Das
28*3590dfbdSTaniya DasallOf:
29*3590dfbdSTaniya Das  - $ref: qcom,gcc.yaml#
30*3590dfbdSTaniya Das
31*3590dfbdSTaniya DasunevaluatedProperties: false
32*3590dfbdSTaniya Das
33*3590dfbdSTaniya Dasexamples:
34*3590dfbdSTaniya Das  - |
35*3590dfbdSTaniya Das    #include <dt-bindings/clock/qcom,rpmh.h>
36*3590dfbdSTaniya Das    #include <dt-bindings/clock/qcom,qcs615-gcc.h>
37*3590dfbdSTaniya Das
38*3590dfbdSTaniya Das    clock-controller@5090000 {
39*3590dfbdSTaniya Das      compatible = "qcom,qcs615-gpucc";
40*3590dfbdSTaniya Das      reg = <0x5090000 0x9000>;
41*3590dfbdSTaniya Das      clocks = <&rpmhcc RPMH_CXO_CLK>,
42*3590dfbdSTaniya Das               <&gcc GPLL0>,
43*3590dfbdSTaniya Das               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
44*3590dfbdSTaniya Das
45*3590dfbdSTaniya Das      #clock-cells = <1>;
46*3590dfbdSTaniya Das      #reset-cells = <1>;
47*3590dfbdSTaniya Das      #power-domain-cells = <1>;
48*3590dfbdSTaniya Das    };
49*3590dfbdSTaniya Das...
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