1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Multimedia Clock & Reset Controller 8 9maintainers: 10 - Jeffrey Hugo <quic_jhugo@quicinc.com> 11 - Taniya Das <quic_tdas@quicinc.com> 12 13description: | 14 Qualcomm multimedia clock control module provides the clocks, resets and 15 power domains. 16 17properties: 18 compatible: 19 enum: 20 - qcom,mmcc-apq8064 21 - qcom,mmcc-apq8084 22 - qcom,mmcc-msm8226 23 - qcom,mmcc-msm8660 24 - qcom,mmcc-msm8960 25 - qcom,mmcc-msm8974 26 - qcom,mmcc-msm8992 27 - qcom,mmcc-msm8994 28 - qcom,mmcc-msm8996 29 - qcom,mmcc-msm8998 30 - qcom,mmcc-sdm630 31 - qcom,mmcc-sdm660 32 33 clocks: 34 minItems: 7 35 maxItems: 13 36 37 clock-names: 38 minItems: 7 39 maxItems: 13 40 41 vdd-gfx-supply: 42 description: 43 Regulator supply for the GPU_GX GDSC 44 45required: 46 - compatible 47 - '#power-domain-cells' 48 49allOf: 50 - $ref: qcom,gcc.yaml# 51 - if: 52 properties: 53 compatible: 54 contains: 55 enum: 56 - qcom,mmcc-apq8064 57 - qcom,mmcc-msm8960 58 then: 59 properties: 60 clocks: 61 minItems: 8 62 items: 63 - description: Board PXO source 64 - description: PLL 3 clock 65 - description: PLL 3 Vote clock 66 - description: DSI phy instance 1 dsi clock 67 - description: DSI phy instance 1 byte clock 68 - description: DSI phy instance 2 dsi clock 69 - description: DSI phy instance 2 byte clock 70 - description: HDMI phy PLL clock 71 - description: LVDS PLL clock 72 73 clock-names: 74 minItems: 8 75 items: 76 - const: pxo 77 - const: pll3 78 - const: pll8_vote 79 - const: dsi1pll 80 - const: dsi1pllbyte 81 - const: dsi2pll 82 - const: dsi2pllbyte 83 - const: hdmipll 84 - const: lvdspll 85 86 - if: 87 properties: 88 compatible: 89 contains: 90 enum: 91 - qcom,mmcc-msm8226 92 then: 93 properties: 94 clocks: 95 items: 96 - description: Board XO source 97 - description: MMSS GPLL0 voted clock 98 - description: GPLL0 voted clock 99 - description: GPLL1 voted clock 100 - description: GFX3D clock source 101 - description: DSI phy instance 0 dsi clock 102 - description: DSI phy instance 0 byte clock 103 104 clock-names: 105 items: 106 - const: xo 107 - const: mmss_gpll0_vote 108 - const: gpll0_vote 109 - const: gpll1_vote 110 - const: gfx3d_clk_src 111 - const: dsi0pll 112 - const: dsi0pllbyte 113 114 - if: 115 properties: 116 compatible: 117 contains: 118 enum: 119 - qcom,mmcc-msm8974 120 then: 121 properties: 122 clocks: 123 items: 124 - description: Board XO source 125 - description: MMSS GPLL0 voted clock 126 - description: GPLL0 voted clock 127 - description: GPLL1 voted clock 128 - description: GFX3D clock source 129 - description: DSI phy instance 0 dsi clock 130 - description: DSI phy instance 0 byte clock 131 - description: DSI phy instance 1 dsi clock 132 - description: DSI phy instance 1 byte clock 133 - description: HDMI phy PLL clock 134 - description: eDP phy PLL link clock 135 - description: eDP phy PLL vco clock 136 137 clock-names: 138 items: 139 - const: xo 140 - const: mmss_gpll0_vote 141 - const: gpll0_vote 142 - const: gpll1_vote 143 - const: gfx3d_clk_src 144 - const: dsi0pll 145 - const: dsi0pllbyte 146 - const: dsi1pll 147 - const: dsi1pllbyte 148 - const: hdmipll 149 - const: edp_link_clk 150 - const: edp_vco_div 151 152 - if: 153 properties: 154 compatible: 155 contains: 156 enum: 157 - qcom,mmcc-apq8084 158 then: 159 properties: 160 clocks: 161 items: 162 - description: Board XO source 163 - description: Board sleep source 164 - description: MMSS GPLL0 voted clock 165 - description: GPLL0 clock 166 - description: GPLL0 voted clock 167 - description: GPLL1 clock 168 - description: DSI phy instance 0 dsi clock 169 - description: DSI phy instance 0 byte clock 170 - description: DSI phy instance 1 dsi clock 171 - description: DSI phy instance 1 byte clock 172 - description: HDMI phy PLL clock 173 - description: eDP phy PLL link clock 174 - description: eDP phy PLL vco clock 175 176 clock-names: 177 items: 178 - const: xo 179 - const: sleep_clk 180 - const: mmss_gpll0_vote 181 - const: gpll0 182 - const: gpll0_vote 183 - const: gpll1 184 - const: dsi0pll 185 - const: dsi0pllbyte 186 - const: dsi1pll 187 - const: dsi1pllbyte 188 - const: hdmipll 189 - const: edp_link_clk 190 - const: edp_vco_div 191 192 - if: 193 properties: 194 compatible: 195 contains: 196 enum: 197 - qcom,mmcc-msm8994 198 - qcom,mmcc-msm8998 199 - qcom,mmcc-sdm630 200 - qcom,mmcc-sdm660 201 then: 202 required: 203 - clocks 204 - clock-names 205 206 - if: 207 properties: 208 compatible: 209 contains: 210 const: qcom,mmcc-msm8994 211 then: 212 properties: 213 clocks: 214 items: 215 - description: Board XO source 216 - description: Global PLL 0 clock 217 - description: MMSS NoC AHB clock 218 - description: GFX3D clock 219 - description: DSI phy instance 0 dsi clock 220 - description: DSI phy instance 0 byte clock 221 - description: DSI phy instance 1 dsi clock 222 - description: DSI phy instance 1 byte clock 223 - description: HDMI phy PLL clock 224 225 clock-names: 226 items: 227 - const: xo 228 - const: gpll0 229 - const: mmssnoc_ahb 230 - const: oxili_gfx3d_clk_src 231 - const: dsi0pll 232 - const: dsi0pllbyte 233 - const: dsi1pll 234 - const: dsi1pllbyte 235 - const: hdmipll 236 237 - if: 238 properties: 239 compatible: 240 contains: 241 const: qcom,mmcc-msm8996 242 then: 243 properties: 244 clocks: 245 items: 246 - description: Board XO source 247 - description: Global PLL 0 clock 248 - description: MMSS NoC AHB clock 249 - description: DSI phy instance 0 dsi clock 250 - description: DSI phy instance 0 byte clock 251 - description: DSI phy instance 1 dsi clock 252 - description: DSI phy instance 1 byte clock 253 - description: HDMI phy PLL clock 254 255 clock-names: 256 items: 257 - const: xo 258 - const: gpll0 259 - const: gcc_mmss_noc_cfg_ahb_clk 260 - const: dsi0pll 261 - const: dsi0pllbyte 262 - const: dsi1pll 263 - const: dsi1pllbyte 264 - const: hdmipll 265 266 - if: 267 properties: 268 compatible: 269 contains: 270 const: qcom,mmcc-msm8998 271 then: 272 properties: 273 clocks: 274 items: 275 - description: Board XO source 276 - description: Global PLL 0 clock 277 - description: DSI phy instance 0 dsi clock 278 - description: DSI phy instance 0 byte clock 279 - description: DSI phy instance 1 dsi clock 280 - description: DSI phy instance 1 byte clock 281 - description: HDMI phy PLL clock 282 - description: DisplayPort phy PLL link clock 283 - description: DisplayPort phy PLL vco clock 284 - description: Global PLL 0 DIV clock 285 286 clock-names: 287 items: 288 - const: xo 289 - const: gpll0 290 - const: dsi0dsi 291 - const: dsi0byte 292 - const: dsi1dsi 293 - const: dsi1byte 294 - const: hdmipll 295 - const: dplink 296 - const: dpvco 297 - const: gpll0_div 298 299 - if: 300 properties: 301 compatible: 302 contains: 303 enum: 304 - qcom,mmcc-sdm630 305 - qcom,mmcc-sdm660 306 then: 307 properties: 308 clocks: 309 items: 310 - description: Board XO source 311 - description: Board sleep source 312 - description: Global PLL 0 clock 313 - description: Global PLL 0 DIV clock 314 - description: DSI phy instance 0 dsi clock 315 - description: DSI phy instance 0 byte clock 316 - description: DSI phy instance 1 dsi clock 317 - description: DSI phy instance 1 byte clock 318 - description: DisplayPort phy PLL link clock 319 - description: DisplayPort phy PLL vco clock 320 321 clock-names: 322 items: 323 - const: xo 324 - const: sleep_clk 325 - const: gpll0 326 - const: gpll0_div 327 - const: dsi0pll 328 - const: dsi0pllbyte 329 - const: dsi1pll 330 - const: dsi1pllbyte 331 - const: dp_link_2x_clk_divsel_five 332 - const: dp_vco_divided_clk_src_mux 333 334unevaluatedProperties: false 335 336examples: 337 # Example for MMCC for MSM8960: 338 - | 339 clock-controller@4000000 { 340 compatible = "qcom,mmcc-msm8960"; 341 reg = <0x4000000 0x1000>; 342 #clock-cells = <1>; 343 #reset-cells = <1>; 344 #power-domain-cells = <1>; 345 }; 346... 347