xref: /linux/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on IPQ9574
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Anusha Rao <quic_anusha@quicinc.com>
12
13description: |
14  Qualcomm global clock control module provides the clocks, resets and power
15  domains on IPQ9574
16
17  See also::
18    include/dt-bindings/clock/qcom,ipq9574-gcc.h
19    include/dt-bindings/reset/qcom,ipq9574-gcc.h
20
21properties:
22  compatible:
23    const: qcom,ipq9574-gcc
24
25  clocks:
26    items:
27      - description: Board XO source
28      - description: Sleep clock source
29      - description: Bias PLL ubi clock source
30      - description: PCIE30 PHY0 pipe clock source
31      - description: PCIE30 PHY1 pipe clock source
32      - description: PCIE30 PHY2 pipe clock source
33      - description: PCIE30 PHY3 pipe clock source
34      - description: USB3 PHY pipe clock source
35
36  '#power-domain-cells': false
37
38  '#interconnect-cells':
39    const: 1
40
41required:
42  - compatible
43  - clocks
44
45allOf:
46  - $ref: qcom,gcc.yaml#
47
48unevaluatedProperties: false
49
50examples:
51  - |
52    clock-controller@1800000 {
53      compatible = "qcom,ipq9574-gcc";
54      reg = <0x01800000 0x80000>;
55      clocks = <&xo_board_clk>,
56               <&sleep_clk>,
57               <&bias_pll_ubi_nc_clk>,
58               <&pcie30_phy0_pipe_clk>,
59               <&pcie30_phy1_pipe_clk>,
60               <&pcie30_phy2_pipe_clk>,
61               <&pcie30_phy3_pipe_clk>,
62               <&usb3phy_0_cc_pipe_clk>;
63      #clock-cells = <1>;
64      #reset-cells = <1>;
65    };
66...
67