1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Graphics Clock & Reset Controller 8 9maintainers: 10 - Taniya Das <quic_tdas@quicinc.com> 11 12description: | 13 Qualcomm graphics clock control module provides the clocks, resets and power 14 domains on Qualcomm SoCs. 15 16 See also:: 17 include/dt-bindings/clock/qcom,gpucc-sdm845.h 18 include/dt-bindings/clock/qcom,gpucc-sa8775p.h 19 include/dt-bindings/clock/qcom,gpucc-sc7180.h 20 include/dt-bindings/clock/qcom,gpucc-sc7280.h 21 include/dt-bindings/clock/qcom,gpucc-sc8280xp.h 22 include/dt-bindings/clock/qcom,gpucc-sm6350.h 23 include/dt-bindings/clock/qcom,gpucc-sm8150.h 24 include/dt-bindings/clock/qcom,gpucc-sm8250.h 25 include/dt-bindings/clock/qcom,gpucc-sm8350.h 26 27properties: 28 compatible: 29 enum: 30 - qcom,sdm845-gpucc 31 - qcom,sa8775p-gpucc 32 - qcom,sc7180-gpucc 33 - qcom,sc7280-gpucc 34 - qcom,sc8180x-gpucc 35 - qcom,sc8280xp-gpucc 36 - qcom,sm6350-gpucc 37 - qcom,sm8150-gpucc 38 - qcom,sm8250-gpucc 39 - qcom,sm8350-gpucc 40 41 clocks: 42 items: 43 - description: Board XO source 44 - description: GPLL0 main branch source 45 - description: GPLL0 div branch source 46 47 clock-names: 48 items: 49 - const: bi_tcxo 50 - const: gcc_gpu_gpll0_clk_src 51 - const: gcc_gpu_gpll0_div_clk_src 52 53 power-domains: 54 maxItems: 1 55 56 vdd-gfx-supply: 57 description: Regulator supply for the VDD_GFX pads 58 59 '#clock-cells': 60 const: 1 61 62 '#reset-cells': 63 const: 1 64 65 '#power-domain-cells': 66 const: 1 67 68 reg: 69 maxItems: 1 70 71required: 72 - compatible 73 - reg 74 - clocks 75 - clock-names 76 - '#clock-cells' 77 - '#reset-cells' 78 - '#power-domain-cells' 79 80# Require that power-domains and vdd-gfx-supply are not both present 81not: 82 required: 83 - power-domains 84 - vdd-gfx-supply 85 86additionalProperties: false 87 88examples: 89 - | 90 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 91 #include <dt-bindings/clock/qcom,rpmh.h> 92 clock-controller@5090000 { 93 compatible = "qcom,sdm845-gpucc"; 94 reg = <0x05090000 0x9000>; 95 clocks = <&rpmhcc RPMH_CXO_CLK>, 96 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 97 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 98 clock-names = "bi_tcxo", 99 "gcc_gpu_gpll0_clk_src", 100 "gcc_gpu_gpll0_div_clk_src"; 101 #clock-cells = <1>; 102 #reset-cells = <1>; 103 #power-domain-cells = <1>; 104 }; 105... 106