1*781c118cSTaniya Das# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*781c118cSTaniya Das%YAML 1.2 3*781c118cSTaniya Das--- 4*781c118cSTaniya Das$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml# 5*781c118cSTaniya Das$schema: http://devicetree.org/meta-schemas/core.yaml# 6*781c118cSTaniya Das 7*781c118cSTaniya Dastitle: Qualcomm Display Clock & Reset Controller on GLYMUR 8*781c118cSTaniya Das 9*781c118cSTaniya Dasmaintainers: 10*781c118cSTaniya Das - Taniya Das <taniya.das@oss.qualcomm.com> 11*781c118cSTaniya Das 12*781c118cSTaniya Dasdescription: | 13*781c118cSTaniya Das Qualcomm display clock control module which supports the clocks, resets and 14*781c118cSTaniya Das power domains for the MDSS instances on GLYMUR SoC. 15*781c118cSTaniya Das 16*781c118cSTaniya Das See also: 17*781c118cSTaniya Das include/dt-bindings/clock/qcom,dispcc-glymur.h 18*781c118cSTaniya Das 19*781c118cSTaniya Dasproperties: 20*781c118cSTaniya Das compatible: 21*781c118cSTaniya Das enum: 22*781c118cSTaniya Das - qcom,glymur-dispcc 23*781c118cSTaniya Das 24*781c118cSTaniya Das clocks: 25*781c118cSTaniya Das items: 26*781c118cSTaniya Das - description: Board CXO clock 27*781c118cSTaniya Das - description: Board sleep clock 28*781c118cSTaniya Das - description: DisplayPort 0 link clock 29*781c118cSTaniya Das - description: DisplayPort 0 VCO div clock 30*781c118cSTaniya Das - description: DisplayPort 1 link clock 31*781c118cSTaniya Das - description: DisplayPort 1 VCO div clock 32*781c118cSTaniya Das - description: DisplayPort 2 link clock 33*781c118cSTaniya Das - description: DisplayPort 2 VCO div clock 34*781c118cSTaniya Das - description: DisplayPort 3 link clock 35*781c118cSTaniya Das - description: DisplayPort 3 VCO div clock 36*781c118cSTaniya Das - description: DSI 0 PLL byte clock 37*781c118cSTaniya Das - description: DSI 0 PLL DSI clock 38*781c118cSTaniya Das - description: DSI 1 PLL byte clock 39*781c118cSTaniya Das - description: DSI 1 PLL DSI clock 40*781c118cSTaniya Das - description: Standalone PHY 0 PLL link clock 41*781c118cSTaniya Das - description: Standalone PHY 0 VCO div clock 42*781c118cSTaniya Das - description: Standalone PHY 1 PLL link clock 43*781c118cSTaniya Das - description: Standalone PHY 1 VCO div clock 44*781c118cSTaniya Das 45*781c118cSTaniya Das power-domains: 46*781c118cSTaniya Das description: 47*781c118cSTaniya Das A phandle and PM domain specifier for the MMCX power domain. 48*781c118cSTaniya Das maxItems: 1 49*781c118cSTaniya Das 50*781c118cSTaniya Das required-opps: 51*781c118cSTaniya Das description: 52*781c118cSTaniya Das A phandle to an OPP node describing required MMCX performance point. 53*781c118cSTaniya Das maxItems: 1 54*781c118cSTaniya Das 55*781c118cSTaniya Dasrequired: 56*781c118cSTaniya Das - compatible 57*781c118cSTaniya Das - clocks 58*781c118cSTaniya Das - power-domains 59*781c118cSTaniya Das - '#power-domain-cells' 60*781c118cSTaniya Das 61*781c118cSTaniya DasallOf: 62*781c118cSTaniya Das - $ref: qcom,gcc.yaml# 63*781c118cSTaniya Das 64*781c118cSTaniya DasunevaluatedProperties: false 65*781c118cSTaniya Das 66*781c118cSTaniya Dasexamples: 67*781c118cSTaniya Das - | 68*781c118cSTaniya Das #include <dt-bindings/clock/qcom,rpmh.h> 69*781c118cSTaniya Das #include <dt-bindings/power/qcom,rpmhpd.h> 70*781c118cSTaniya Das 71*781c118cSTaniya Das clock-controller@af00000 { 72*781c118cSTaniya Das compatible = "qcom,glymur-dispcc"; 73*781c118cSTaniya Das reg = <0x0af00000 0x20000>; 74*781c118cSTaniya Das clocks = <&rpmhcc RPMH_CXO_CLK>, 75*781c118cSTaniya Das <&sleep_clk>, 76*781c118cSTaniya Das <&mdss_dp_phy0 0>, 77*781c118cSTaniya Das <&mdss_dp_phy0 1>, 78*781c118cSTaniya Das <&mdss_dp_phy1 0>, 79*781c118cSTaniya Das <&mdss_dp_phy1 1>, 80*781c118cSTaniya Das <&mdss_dp_phy2 0>, 81*781c118cSTaniya Das <&mdss_dp_phy2 1>, 82*781c118cSTaniya Das <&mdss_dp_phy3 0>, 83*781c118cSTaniya Das <&mdss_dp_phy3 1>, 84*781c118cSTaniya Das <&mdss_dsi0_phy 0>, 85*781c118cSTaniya Das <&mdss_dsi0_phy 1>, 86*781c118cSTaniya Das <&mdss_dsi1_phy 0>, 87*781c118cSTaniya Das <&mdss_dsi1_phy 1>, 88*781c118cSTaniya Das <&mdss_phy0_link 0>, 89*781c118cSTaniya Das <&mdss_phy0_vco_div 0>, 90*781c118cSTaniya Das <&mdss_phy1_link 1>, 91*781c118cSTaniya Das <&mdss_phy1_vco_div 1>; 92*781c118cSTaniya Das power-domains = <&rpmhpd RPMHPD_MMCX>; 93*781c118cSTaniya Das required-opps = <&rpmhpd_opp_low_svs>; 94*781c118cSTaniya Das #clock-cells = <1>; 95*781c118cSTaniya Das #reset-cells = <1>; 96*781c118cSTaniya Das #power-domain-cells = <1>; 97*781c118cSTaniya Das }; 98*781c118cSTaniya Das... 99