xref: /linux/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml (revision 7f4f3b14e8079ecde096bd734af10e30d40c27b7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on SM8450
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description: |
13  Qualcomm global clock control module provides the clocks, resets and power
14  domains on SM8450
15
16  See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h
17
18properties:
19  compatible:
20    enum:
21      - qcom,gcc-sm8450
22      - qcom,sm8475-gcc
23
24  clocks:
25    items:
26      - description: Board XO source
27      - description: Sleep clock source
28      - description: PCIE 0 Pipe clock source (Optional clock)
29      - description: PCIE 1 Pipe clock source (Optional clock)
30      - description: PCIE 1 Phy Auxiliary clock source (Optional clock)
31      - description: UFS Phy Rx symbol 0 clock source (Optional clock)
32      - description: UFS Phy Rx symbol 1 clock source (Optional clock)
33      - description: UFS Phy Tx symbol 0 clock source (Optional clock)
34      - description: USB3 Phy wrapper pipe clock source (Optional clock)
35    minItems: 2
36
37  clock-names:
38    items:
39      - const: bi_tcxo
40      - const: sleep_clk
41      - const: pcie_0_pipe_clk # Optional clock
42      - const: pcie_1_pipe_clk # Optional clock
43      - const: pcie_1_phy_aux_clk # Optional clock
44      - const: ufs_phy_rx_symbol_0_clk # Optional clock
45      - const: ufs_phy_rx_symbol_1_clk # Optional clock
46      - const: ufs_phy_tx_symbol_0_clk # Optional clock
47      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
48    minItems: 2
49
50required:
51  - compatible
52  - clocks
53  - clock-names
54  - '#power-domain-cells'
55
56allOf:
57  - $ref: qcom,gcc.yaml#
58
59unevaluatedProperties: false
60
61examples:
62  - |
63    #include <dt-bindings/clock/qcom,rpmh.h>
64    clock-controller@100000 {
65      compatible = "qcom,gcc-sm8450";
66      reg = <0x00100000 0x001f4200>;
67      clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
68      clock-names = "bi_tcxo", "sleep_clk";
69      #clock-cells = <1>;
70      #reset-cells = <1>;
71      #power-domain-cells = <1>;
72    };
73
74...
75