xref: /linux/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml (revision 24bce201d79807b668bf9d9e0aca801c5c0d5f78) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller Binding for SM8350
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description: |
13  Qualcomm global clock control module which supports the clocks, resets and
14  power domains on SM8350.
15
16  See also:
17  - dt-bindings/clock/qcom,gcc-sm8350.h
18
19properties:
20  compatible:
21    const: qcom,gcc-sm8350
22
23  clocks:
24    items:
25      - description: Board XO source
26      - description: Sleep clock source
27      - description: PLL test clock source (Optional clock)
28      - description: PCIE 0 Pipe clock source (Optional clock)
29      - description: PCIE 1 Pipe clock source (Optional clock)
30      - description: UFS card Rx symbol 0 clock source (Optional clock)
31      - description: UFS card Rx symbol 1 clock source (Optional clock)
32      - description: UFS card Tx symbol 0 clock source (Optional clock)
33      - description: UFS phy Rx symbol 0 clock source (Optional clock)
34      - description: UFS phy Rx symbol 1 clock source (Optional clock)
35      - description: UFS phy Tx symbol 0 clock source (Optional clock)
36      - description: USB3 phy wrapper pipe clock source (Optional clock)
37      - description: USB3 phy sec pipe clock source (Optional clock)
38    minItems: 2
39
40  clock-names:
41    items:
42      - const: bi_tcxo
43      - const: sleep_clk
44      - const: core_bi_pll_test_se # Optional clock
45      - const: pcie_0_pipe_clk # Optional clock
46      - const: pcie_1_pipe_clk # Optional clock
47      - const: ufs_card_rx_symbol_0_clk # Optional clock
48      - const: ufs_card_rx_symbol_1_clk # Optional clock
49      - const: ufs_card_tx_symbol_0_clk # Optional clock
50      - const: ufs_phy_rx_symbol_0_clk # Optional clock
51      - const: ufs_phy_rx_symbol_1_clk # Optional clock
52      - const: ufs_phy_tx_symbol_0_clk # Optional clock
53      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
54      - const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
55    minItems: 2
56
57  '#clock-cells':
58    const: 1
59
60  '#reset-cells':
61    const: 1
62
63  '#power-domain-cells':
64    const: 1
65
66  reg:
67    maxItems: 1
68
69required:
70  - compatible
71  - clocks
72  - clock-names
73  - reg
74  - '#clock-cells'
75  - '#reset-cells'
76  - '#power-domain-cells'
77
78additionalProperties: false
79
80examples:
81  - |
82    #include <dt-bindings/clock/qcom,rpmh.h>
83    clock-controller@100000 {
84      compatible = "qcom,gcc-sm8350";
85      reg = <0x00100000 0x1f0000>;
86      clocks = <&rpmhcc RPMH_CXO_CLK>,
87               <&sleep_clk>;
88      clock-names = "bi_tcxo", "sleep_clk";
89      #clock-cells = <1>;
90      #reset-cells = <1>;
91      #power-domain-cells = <1>;
92    };
93
94...
95