xref: /linux/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml (revision 55d0969c451159cff86949b38c39171cab962069) 
1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8996.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on MSM8996
8
9maintainers:
10  - Stephen Boyd <sboyd@kernel.org>
11  - Taniya Das <quic_tdas@quicinc.com>
12
13description: |
14  Qualcomm global clock control module which provides the clocks, resets and
15  power domains on MSM8996.
16
17  See also:: include/dt-bindings/clock/qcom,gcc-msm8996.h
18
19properties:
20  compatible:
21    const: qcom,gcc-msm8996
22
23  clocks:
24    minItems: 3
25    items:
26      - description: XO source
27      - description: Second XO source
28      - description: Sleep clock source
29      - description: PCIe 0 PIPE clock (optional)
30      - description: PCIe 1 PIPE clock (optional)
31      - description: PCIe 2 PIPE clock (optional)
32      - description: USB3 PIPE clock (optional)
33      - description: UFS RX symbol 0 clock (optional)
34      - description: UFS RX symbol 1 clock (optional)
35      - description: UFS TX symbol 0 clock (optional)
36
37  clock-names:
38    minItems: 3
39    items:
40      - const: cxo
41      - const: cxo2
42      - const: sleep_clk
43      - const: pcie_0_pipe_clk_src
44      - const: pcie_1_pipe_clk_src
45      - const: pcie_2_pipe_clk_src
46      - const: usb3_phy_pipe_clk_src
47      - const: ufs_rx_symbol_0_clk_src
48      - const: ufs_rx_symbol_1_clk_src
49      - const: ufs_tx_symbol_0_clk_src
50
51required:
52  - compatible
53  - '#power-domain-cells'
54
55allOf:
56  - $ref: qcom,gcc.yaml#
57
58unevaluatedProperties: false
59
60examples:
61  - |
62    clock-controller@300000 {
63      compatible = "qcom,gcc-msm8996";
64      #clock-cells = <1>;
65      #reset-cells = <1>;
66      #power-domain-cells = <1>;
67      reg = <0x300000 0x90000>;
68    };
69...
70