1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Global Clock & Reset Controller on MSM8953 8 9maintainers: 10 - Adam Skladowski <a_skl39@protonmail.com> 11 - Sireesh Kodali <sireeshkodali@protonmail.com> 12 13description: | 14 Qualcomm global clock control module provides the clocks, resets and power 15 domains on MSM8953. 16 17 See also: include/dt-bindings/clock/qcom,gcc-msm8953.h 18 19properties: 20 compatible: 21 const: qcom,gcc-msm8953 22 23 clocks: 24 items: 25 - description: Board XO source 26 - description: Sleep clock source 27 - description: Byte clock from DSI PHY0 28 - description: Pixel clock from DSI PHY0 29 - description: Byte clock from DSI PHY1 30 - description: Pixel clock from DSI PHY1 31 32 clock-names: 33 items: 34 - const: xo 35 - const: sleep 36 - const: dsi0pll 37 - const: dsi0pllbyte 38 - const: dsi1pll 39 - const: dsi1pllbyte 40 41required: 42 - compatible 43 - clocks 44 - clock-names 45 46allOf: 47 - $ref: qcom,gcc.yaml# 48 49unevaluatedProperties: false 50 51examples: 52 - | 53 #include <dt-bindings/clock/qcom,rpmcc.h> 54 55 clock-controller@1800000 { 56 compatible = "qcom,gcc-msm8953"; 57 reg = <0x01800000 0x80000>; 58 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 59 <&sleep_clk>, 60 <&dsi0_phy 1>, 61 <&dsi0_phy 0>, 62 <&dsi1_phy 1>, 63 <&dsi1_phy 0>; 64 clock-names = "xo", 65 "sleep", 66 "dsi0pll", 67 "dsi0pllbyte", 68 "dsi1pll", 69 "dsi1pllbyte"; 70 #clock-cells = <1>; 71 #reset-cells = <1>; 72 #power-domain-cells = <1>; 73 }; 74