xref: /linux/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml (revision 156010ed9c2ac1e9df6c11b1f688cf8a6e0152e6) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display Clock Controller on SM6125
8
9maintainers:
10  - Martin Botka <martin.botka@somainline.org>
11
12description: |
13  Qualcomm display clock control module provides the clocks and power domains
14  on SM6125.
15
16  See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h
17
18properties:
19  compatible:
20    enum:
21      - qcom,sm6125-dispcc
22
23  clocks:
24    items:
25      - description: Board XO source
26      - description: Byte clock from DSI PHY0
27      - description: Pixel clock from DSI PHY0
28      - description: Pixel clock from DSI PHY1
29      - description: Link clock from DP PHY
30      - description: VCO DIV clock from DP PHY
31      - description: AHB config clock from GCC
32
33  clock-names:
34    items:
35      - const: bi_tcxo
36      - const: dsi0_phy_pll_out_byteclk
37      - const: dsi0_phy_pll_out_dsiclk
38      - const: dsi1_phy_pll_out_dsiclk
39      - const: dp_phy_pll_link_clk
40      - const: dp_phy_pll_vco_div_clk
41      - const: cfg_ahb_clk
42
43  '#clock-cells':
44    const: 1
45
46  '#power-domain-cells':
47    const: 1
48
49  reg:
50    maxItems: 1
51
52required:
53  - compatible
54  - reg
55  - clocks
56  - clock-names
57  - '#clock-cells'
58  - '#power-domain-cells'
59
60additionalProperties: false
61
62examples:
63  - |
64    #include <dt-bindings/clock/qcom,rpmcc.h>
65    #include <dt-bindings/clock/qcom,gcc-sm6125.h>
66    clock-controller@5f00000 {
67      compatible = "qcom,sm6125-dispcc";
68      reg = <0x5f00000 0x20000>;
69      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
70               <&dsi0_phy 0>,
71               <&dsi0_phy 1>,
72               <&dsi1_phy 1>,
73               <&dp_phy 0>,
74               <&dp_phy 1>,
75               <&gcc GCC_DISP_AHB_CLK>;
76      clock-names = "bi_tcxo",
77                    "dsi0_phy_pll_out_byteclk",
78                    "dsi0_phy_pll_out_dsiclk",
79                    "dsi1_phy_pll_out_dsiclk",
80                    "dp_phy_pll_link_clk",
81                    "dp_phy_pll_vco_div_clk",
82                    "cfg_ahb_clk";
83      #clock-cells = <1>;
84      #power-domain-cells = <1>;
85    };
86...
87