xref: /linux/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml (revision 0a94608f0f7de9b1135ffea3546afe68eafef57f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display Clock Controller Binding for SM6125
8
9maintainers:
10  - Martin Botka <martin.botka@somainline.org>
11
12description: |
13  Qualcomm display clock control module which supports the clocks and
14  power domains on SM6125.
15
16  See also:
17    dt-bindings/clock/qcom,dispcc-sm6125.h
18
19properties:
20  compatible:
21    enum:
22      - qcom,sm6125-dispcc
23
24  clocks:
25    items:
26      - description: Board XO source
27      - description: Byte clock from DSI PHY0
28      - description: Pixel clock from DSI PHY0
29      - description: Pixel clock from DSI PHY1
30      - description: Link clock from DP PHY
31      - description: VCO DIV clock from DP PHY
32      - description: AHB config clock from GCC
33
34  clock-names:
35    items:
36      - const: bi_tcxo
37      - const: dsi0_phy_pll_out_byteclk
38      - const: dsi0_phy_pll_out_dsiclk
39      - const: dsi1_phy_pll_out_dsiclk
40      - const: dp_phy_pll_link_clk
41      - const: dp_phy_pll_vco_div_clk
42      - const: cfg_ahb_clk
43
44  '#clock-cells':
45    const: 1
46
47  '#power-domain-cells':
48    const: 1
49
50  reg:
51    maxItems: 1
52
53required:
54  - compatible
55  - reg
56  - clocks
57  - clock-names
58  - '#clock-cells'
59  - '#power-domain-cells'
60
61additionalProperties: false
62
63examples:
64  - |
65    #include <dt-bindings/clock/qcom,rpmcc.h>
66    #include <dt-bindings/clock/qcom,gcc-sm6125.h>
67    clock-controller@5f00000 {
68      compatible = "qcom,sm6125-dispcc";
69      reg = <0x5f00000 0x20000>;
70      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
71               <&dsi0_phy 0>,
72               <&dsi0_phy 1>,
73               <&dsi1_phy 1>,
74               <&dp_phy 0>,
75               <&dp_phy 1>,
76               <&gcc GCC_DISP_AHB_CLK>;
77      clock-names = "bi_tcxo",
78                    "dsi0_phy_pll_out_byteclk",
79                    "dsi0_phy_pll_out_dsiclk",
80                    "dsi1_phy_pll_out_dsiclk",
81                    "dp_phy_pll_link_clk",
82                    "dp_phy_pll_vco_div_clk",
83                    "cfg_ahb_clk";
84      #clock-cells = <1>;
85      #power-domain-cells = <1>;
86    };
87...
88