xref: /linux/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml (revision f057b57270c2a17d3f45c177e9434fa5745caa48) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Graphics Clock & Reset Controller on SM8450
8
9maintainers:
10  - Konrad Dybcio <konradybcio@kernel.org>
11
12description: |
13  Qualcomm graphics clock control module provides the clocks, resets and power
14  domains on Qualcomm SoCs.
15
16  See also::
17    include/dt-bindings/clock/qcom,sm8450-gpucc.h
18    include/dt-bindings/clock/qcom,sm8550-gpucc.h
19    include/dt-bindings/reset/qcom,sm8450-gpucc.h
20    include/dt-bindings/reset/qcom,sm8650-gpucc.h
21    include/dt-bindings/reset/qcom,x1e80100-gpucc.h
22
23properties:
24  compatible:
25    enum:
26      - qcom,sm8450-gpucc
27      - qcom,sm8550-gpucc
28      - qcom,sm8650-gpucc
29      - qcom,x1e80100-gpucc
30
31  clocks:
32    items:
33      - description: Board XO source
34      - description: GPLL0 main branch source
35      - description: GPLL0 div branch source
36
37required:
38  - compatible
39  - clocks
40  - '#power-domain-cells'
41
42allOf:
43  - $ref: qcom,gcc.yaml#
44
45unevaluatedProperties: false
46
47examples:
48  - |
49    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
50    #include <dt-bindings/clock/qcom,rpmh.h>
51
52    soc {
53        #address-cells = <2>;
54        #size-cells = <2>;
55
56        clock-controller@3d90000 {
57            compatible = "qcom,sm8450-gpucc";
58            reg = <0 0x03d90000 0 0xa000>;
59            clocks = <&rpmhcc RPMH_CXO_CLK>,
60                     <&gcc GCC_GPU_GPLL0_CLK_SRC>,
61                     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
62            #clock-cells = <1>;
63            #reset-cells = <1>;
64            #power-domain-cells = <1>;
65        };
66    };
67...
68