138557c6fSAdam Skladowski# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 238557c6fSAdam Skladowski%YAML 1.2 338557c6fSAdam Skladowski--- 438557c6fSAdam Skladowski$id: http://devicetree.org/schemas/clock/qcom,sm6115-dispcc.yaml# 538557c6fSAdam Skladowski$schema: http://devicetree.org/meta-schemas/core.yaml# 638557c6fSAdam Skladowski 738557c6fSAdam Skladowskititle: Qualcomm Display Clock Controller for SM6115 838557c6fSAdam Skladowski 938557c6fSAdam Skladowskimaintainers: 1038557c6fSAdam Skladowski - Bjorn Andersson <andersson@kernel.org> 1138557c6fSAdam Skladowski 1238557c6fSAdam Skladowskidescription: | 13ece3c319SKrzysztof Kozlowski Qualcomm display clock control module provides the clocks and power domains 14ece3c319SKrzysztof Kozlowski on SM6115. 1538557c6fSAdam Skladowski 16ece3c319SKrzysztof Kozlowski See also:: include/dt-bindings/clock/qcom,sm6115-dispcc.h 1738557c6fSAdam Skladowski 1838557c6fSAdam Skladowskiproperties: 1938557c6fSAdam Skladowski compatible: 2038557c6fSAdam Skladowski enum: 2138557c6fSAdam Skladowski - qcom,sm6115-dispcc 2238557c6fSAdam Skladowski 2338557c6fSAdam Skladowski clocks: 2438557c6fSAdam Skladowski items: 2538557c6fSAdam Skladowski - description: Board XO source 2638557c6fSAdam Skladowski - description: Board sleep clock 2738557c6fSAdam Skladowski - description: Byte clock from DSI PHY0 2838557c6fSAdam Skladowski - description: Pixel clock from DSI PHY0 2938557c6fSAdam Skladowski - description: GPLL0 DISP DIV clock from GCC 3038557c6fSAdam Skladowski 3138557c6fSAdam Skladowskirequired: 3238557c6fSAdam Skladowski - compatible 3338557c6fSAdam Skladowski - clocks 3438557c6fSAdam Skladowski - '#power-domain-cells' 3538557c6fSAdam Skladowski 36*7b69a903SKrzysztof KozlowskiallOf: 37*7b69a903SKrzysztof Kozlowski - $ref: qcom,gcc.yaml# 38*7b69a903SKrzysztof Kozlowski 39*7b69a903SKrzysztof KozlowskiunevaluatedProperties: false 4038557c6fSAdam Skladowski 4138557c6fSAdam Skladowskiexamples: 4238557c6fSAdam Skladowski - | 4338557c6fSAdam Skladowski #include <dt-bindings/clock/qcom,rpmcc.h> 4438557c6fSAdam Skladowski #include <dt-bindings/clock/qcom,gcc-sm6115.h> 4538557c6fSAdam Skladowski clock-controller@5f00000 { 4638557c6fSAdam Skladowski compatible = "qcom,sm6115-dispcc"; 4738557c6fSAdam Skladowski reg = <0x5f00000 0x20000>; 4838557c6fSAdam Skladowski clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 4938557c6fSAdam Skladowski <&sleep_clk>, 5038557c6fSAdam Skladowski <&dsi0_phy 0>, 5138557c6fSAdam Skladowski <&dsi0_phy 1>, 5238557c6fSAdam Skladowski <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 5338557c6fSAdam Skladowski #clock-cells = <1>; 5438557c6fSAdam Skladowski #reset-cells = <1>; 5538557c6fSAdam Skladowski #power-domain-cells = <1>; 5638557c6fSAdam Skladowski }; 5738557c6fSAdam Skladowski... 58