xref: /linux/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml (revision ff32fcca64437f679a2bf1c0a19d5def389a18e2) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm LPASS Core Clock Controller on SC7280
8
9maintainers:
10  - Taniya Das <tdas@codeaurora.org>
11
12description: |
13  Qualcomm LPASS core clock control module provides the clocks and power
14  domains on SC7280.
15
16  See also:: include/dt-bindings/clock/qcom,lpass-sc7280.h
17
18properties:
19  compatible:
20    enum:
21      - qcom,sc7280-lpasscc
22
23  clocks:
24    items:
25      - description: gcc_cfg_noc_lpass_clk from GCC
26
27  clock-names:
28    items:
29      - const: iface
30
31  '#clock-cells':
32    const: 1
33
34  reg:
35    items:
36      - description: LPASS qdsp6ss register
37      - description: LPASS top-cc register
38
39  reg-names:
40    items:
41      - const: qdsp6ss
42      - const: top_cc
43
44  qcom,adsp-pil-mode:
45    description:
46      Indicates if the LPASS would be brought out of reset using
47      remoteproc peripheral loader.
48    type: boolean
49
50required:
51  - compatible
52  - reg
53  - clocks
54  - clock-names
55  - '#clock-cells'
56
57additionalProperties: false
58
59examples:
60  - |
61    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
62    #include <dt-bindings/clock/qcom,lpass-sc7280.h>
63    clock-controller@3000000 {
64      compatible = "qcom,sc7280-lpasscc";
65      reg = <0x03000000 0x40>, <0x03c04000 0x4>;
66      reg-names = "qdsp6ss", "top_cc";
67      clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
68      clock-names = "iface";
69      qcom,adsp-pil-mode;
70      #clock-cells = <1>;
71    };
72...
73