148cabc22SDouglas Anderson# SPDX-License-Identifier: GPL-2.0-only 248cabc22SDouglas Anderson%YAML 1.2 348cabc22SDouglas Anderson--- 448cabc22SDouglas Anderson$id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml# 548cabc22SDouglas Anderson$schema: http://devicetree.org/meta-schemas/core.yaml# 648cabc22SDouglas Anderson 7ece3c319SKrzysztof Kozlowskititle: Qualcomm Display Clock & Reset Controller on SC7180 848cabc22SDouglas Anderson 948cabc22SDouglas Andersonmaintainers: 1060838878STaniya Das - Taniya Das <quic_tdas@quicinc.com> 1148cabc22SDouglas Anderson 1248cabc22SDouglas Andersondescription: | 13ece3c319SKrzysztof Kozlowski Qualcomm display clock control module provides the clocks, resets and power 14ece3c319SKrzysztof Kozlowski domains on SC7180. 1548cabc22SDouglas Anderson 16ece3c319SKrzysztof Kozlowski See also:: include/dt-bindings/clock/qcom,dispcc-sc7180.h 1748cabc22SDouglas Anderson 1848cabc22SDouglas Andersonproperties: 1948cabc22SDouglas Anderson compatible: 2048cabc22SDouglas Anderson const: qcom,sc7180-dispcc 2148cabc22SDouglas Anderson 2248cabc22SDouglas Anderson clocks: 2348cabc22SDouglas Anderson items: 2448cabc22SDouglas Anderson - description: Board XO source 2548cabc22SDouglas Anderson - description: GPLL0 source from GCC 2648cabc22SDouglas Anderson - description: Byte clock from DSI PHY 2748cabc22SDouglas Anderson - description: Pixel clock from DSI PHY 2848cabc22SDouglas Anderson - description: Link clock from DP PHY 2948cabc22SDouglas Anderson - description: VCO DIV clock from DP PHY 3048cabc22SDouglas Anderson 3148cabc22SDouglas Anderson clock-names: 3248cabc22SDouglas Anderson items: 3348cabc22SDouglas Anderson - const: bi_tcxo 3448cabc22SDouglas Anderson - const: gcc_disp_gpll0_clk_src 3548cabc22SDouglas Anderson - const: dsi0_phy_pll_out_byteclk 3648cabc22SDouglas Anderson - const: dsi0_phy_pll_out_dsiclk 3748cabc22SDouglas Anderson - const: dp_phy_pll_link_clk 3848cabc22SDouglas Anderson - const: dp_phy_pll_vco_div_clk 3948cabc22SDouglas Anderson 4048cabc22SDouglas Andersonrequired: 4148cabc22SDouglas Anderson - compatible 4248cabc22SDouglas Anderson - clocks 4348cabc22SDouglas Anderson - clock-names 4448cabc22SDouglas Anderson - '#power-domain-cells' 4548cabc22SDouglas Anderson 46*e68a21bdSKrzysztof KozlowskiallOf: 47*e68a21bdSKrzysztof Kozlowski - $ref: qcom,gcc.yaml# 48*e68a21bdSKrzysztof Kozlowski 49*e68a21bdSKrzysztof KozlowskiunevaluatedProperties: false 507f464532SRob Herring 5148cabc22SDouglas Andersonexamples: 5248cabc22SDouglas Anderson - | 5348cabc22SDouglas Anderson #include <dt-bindings/clock/qcom,gcc-sc7180.h> 5448cabc22SDouglas Anderson #include <dt-bindings/clock/qcom,rpmh.h> 5548cabc22SDouglas Anderson clock-controller@af00000 { 5648cabc22SDouglas Anderson compatible = "qcom,sc7180-dispcc"; 57fba56184SRob Herring reg = <0x0af00000 0x200000>; 5848cabc22SDouglas Anderson clocks = <&rpmhcc RPMH_CXO_CLK>, 5948cabc22SDouglas Anderson <&gcc GCC_DISP_GPLL0_CLK_SRC>, 6048cabc22SDouglas Anderson <&dsi_phy 0>, 6148cabc22SDouglas Anderson <&dsi_phy 1>, 6248cabc22SDouglas Anderson <&dp_phy 0>, 6348cabc22SDouglas Anderson <&dp_phy 1>; 6448cabc22SDouglas Anderson clock-names = "bi_tcxo", 6548cabc22SDouglas Anderson "gcc_disp_gpll0_clk_src", 6648cabc22SDouglas Anderson "dsi0_phy_pll_out_byteclk", 6748cabc22SDouglas Anderson "dsi0_phy_pll_out_dsiclk", 6848cabc22SDouglas Anderson "dp_phy_pll_link_clk", 6948cabc22SDouglas Anderson "dp_phy_pll_vco_div_clk"; 7048cabc22SDouglas Anderson #clock-cells = <1>; 7148cabc22SDouglas Anderson #reset-cells = <1>; 7248cabc22SDouglas Anderson #power-domain-cells = <1>; 7348cabc22SDouglas Anderson }; 7448cabc22SDouglas Anderson... 75