1*d4a599c5SImran Shaik# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*d4a599c5SImran Shaik%YAML 1.2 3*d4a599c5SImran Shaik--- 4*d4a599c5SImran Shaik$id: http://devicetree.org/schemas/clock/qcom,qdu1000-ecpricc.yaml# 5*d4a599c5SImran Shaik$schema: http://devicetree.org/meta-schemas/core.yaml# 6*d4a599c5SImran Shaik 7*d4a599c5SImran Shaiktitle: Qualcomm ECPRI Clock & Reset Controller for QDU1000 and QRU1000 8*d4a599c5SImran Shaik 9*d4a599c5SImran Shaikmaintainers: 10*d4a599c5SImran Shaik - Taniya Das <quic_tdas@quicinc.com> 11*d4a599c5SImran Shaik - Imran Shaik <quic_imrashai@quicinc.com> 12*d4a599c5SImran Shaik 13*d4a599c5SImran Shaikdescription: | 14*d4a599c5SImran Shaik Qualcomm ECPRI Specification V2.0 Common Public Radio Interface clock control 15*d4a599c5SImran Shaik module which supports the clocks, resets on QDU1000 and QRU1000 16*d4a599c5SImran Shaik 17*d4a599c5SImran Shaik See also:: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h 18*d4a599c5SImran Shaik 19*d4a599c5SImran Shaikproperties: 20*d4a599c5SImran Shaik compatible: 21*d4a599c5SImran Shaik enum: 22*d4a599c5SImran Shaik - qcom,qdu1000-ecpricc 23*d4a599c5SImran Shaik 24*d4a599c5SImran Shaik reg: 25*d4a599c5SImran Shaik maxItems: 1 26*d4a599c5SImran Shaik 27*d4a599c5SImran Shaik clocks: 28*d4a599c5SImran Shaik items: 29*d4a599c5SImran Shaik - description: Board XO source 30*d4a599c5SImran Shaik - description: GPLL0 source from GCC 31*d4a599c5SImran Shaik - description: GPLL1 source from GCC 32*d4a599c5SImran Shaik - description: GPLL2 source from GCC 33*d4a599c5SImran Shaik - description: GPLL3 source from GCC 34*d4a599c5SImran Shaik - description: GPLL4 source from GCC 35*d4a599c5SImran Shaik - description: GPLL5 source from GCC 36*d4a599c5SImran Shaik 37*d4a599c5SImran Shaik '#clock-cells': 38*d4a599c5SImran Shaik const: 1 39*d4a599c5SImran Shaik 40*d4a599c5SImran Shaik '#reset-cells': 41*d4a599c5SImran Shaik const: 1 42*d4a599c5SImran Shaik 43*d4a599c5SImran Shaikrequired: 44*d4a599c5SImran Shaik - compatible 45*d4a599c5SImran Shaik - reg 46*d4a599c5SImran Shaik - clocks 47*d4a599c5SImran Shaik - '#clock-cells' 48*d4a599c5SImran Shaik - '#reset-cells' 49*d4a599c5SImran Shaik 50*d4a599c5SImran ShaikadditionalProperties: false 51*d4a599c5SImran Shaik 52*d4a599c5SImran Shaikexamples: 53*d4a599c5SImran Shaik - | 54*d4a599c5SImran Shaik #include <dt-bindings/clock/qcom,qdu1000-gcc.h> 55*d4a599c5SImran Shaik #include <dt-bindings/clock/qcom,rpmh.h> 56*d4a599c5SImran Shaik clock-controller@280000 { 57*d4a599c5SImran Shaik compatible = "qcom,qdu1000-ecpricc"; 58*d4a599c5SImran Shaik reg = <0x00280000 0x31c00>; 59*d4a599c5SImran Shaik clocks = <&rpmhcc RPMH_CXO_CLK>, 60*d4a599c5SImran Shaik <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>, 61*d4a599c5SImran Shaik <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>, 62*d4a599c5SImran Shaik <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>, 63*d4a599c5SImran Shaik <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>, 64*d4a599c5SImran Shaik <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>, 65*d4a599c5SImran Shaik <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>; 66*d4a599c5SImran Shaik #clock-cells = <1>; 67*d4a599c5SImran Shaik #reset-cells = <1>; 68*d4a599c5SImran Shaik }; 69