xref: /linux/Documentation/devicetree/bindings/clock/qcom,qcs8300-gcc.yaml (revision 21a5352dc702d8e6dc874e0eb6ba6d81291a788a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,qcs8300-gcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. Global Clock & Reset Controller on QCS8300
8
9maintainers:
10  - Taniya Das <quic_tdas@quicinc.com>
11  - Imran Shaik <quic_imrashai@quicinc.com>
12
13description: |
14  Qualcomm Technologies, Inc. Global clock control module provides the clocks, resets and
15  power domains on QCS8300
16
17  See also: include/dt-bindings/clock/qcom,qcs8300-gcc.h
18
19properties:
20  compatible:
21    const: qcom,qcs8300-gcc
22
23  clocks:
24    items:
25      - description: Board XO source
26      - description: Sleep clock source
27      - description: PCIE 0 Pipe clock source
28      - description: PCIE 1 Pipe clock source
29      - description: PCIE Phy Auxiliary clock source
30      - description: First EMAC controller reference clock
31      - description: UFS Phy Rx symbol 0 clock source
32      - description: UFS Phy Rx symbol 1 clock source
33      - description: UFS Phy Tx symbol 0 clock source
34      - description: USB3 Phy wrapper pipe clock source
35
36required:
37  - compatible
38  - clocks
39  - '#power-domain-cells'
40
41allOf:
42  - $ref: qcom,gcc.yaml#
43
44unevaluatedProperties: false
45
46examples:
47  - |
48    #include <dt-bindings/clock/qcom,rpmh.h>
49    clock-controller@100000 {
50      compatible = "qcom,qcs8300-gcc";
51      reg = <0x00100000 0xc7018>;
52      clocks = <&rpmhcc RPMH_CXO_CLK>,
53               <&sleep_clk>,
54               <&pcie_0_pipe_clk>,
55               <&pcie_1_pipe_clk>,
56               <&pcie_phy_aux_clk>,
57               <&rxc0_ref_clk>,
58               <&ufs_phy_rx_symbol_0_clk>,
59               <&ufs_phy_rx_symbol_1_clk>,
60               <&ufs_phy_tx_symbol_0_clk>,
61               <&usb3_phy_wrapper_gcc_usb30_prim_pipe_clk>;
62      #clock-cells = <1>;
63      #reset-cells = <1>;
64      #power-domain-cells = <1>;
65    };
66...
67