xref: /linux/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml (revision 2c55d703391acf7e9101da596d0c15ee03b318a3) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display Clock & Reset Controller on QCM2290
8
9maintainers:
10  - Loic Poulain <loic.poulain@linaro.org>
11
12description: |
13  Qualcomm display clock control module provides the clocks, resets and power
14  domains on qcm2290.
15
16  See also:: include/dt-bindings/clock/qcom,dispcc-qcm2290.h
17
18properties:
19  compatible:
20    const: qcom,qcm2290-dispcc
21
22  clocks:
23    items:
24      - description: Board XO source
25      - description: Board active-only XO source
26      - description: GPLL0 source from GCC
27      - description: GPLL0 div source from GCC
28      - description: Byte clock from DSI PHY
29      - description: Pixel clock from DSI PHY
30
31  clock-names:
32    items:
33      - const: bi_tcxo
34      - const: bi_tcxo_ao
35      - const: gcc_disp_gpll0_clk_src
36      - const: gcc_disp_gpll0_div_clk_src
37      - const: dsi0_phy_pll_out_byteclk
38      - const: dsi0_phy_pll_out_dsiclk
39
40  '#clock-cells':
41    const: 1
42
43  '#reset-cells':
44    const: 1
45
46  '#power-domain-cells':
47    const: 1
48
49  reg:
50    maxItems: 1
51
52required:
53  - compatible
54  - reg
55  - clocks
56  - clock-names
57  - '#clock-cells'
58  - '#reset-cells'
59  - '#power-domain-cells'
60
61additionalProperties: false
62
63examples:
64  - |
65    #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
66    #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
67    #include <dt-bindings/clock/qcom,rpmcc.h>
68    clock-controller@5f00000 {
69            compatible = "qcom,qcm2290-dispcc";
70            reg = <0x5f00000 0x20000>;
71            clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
72                     <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
73                     <&gcc GCC_DISP_GPLL0_CLK_SRC>,
74                     <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
75                     <&dsi0_phy 0>,
76                     <&dsi0_phy 1>;
77            clock-names = "bi_tcxo",
78                          "bi_tcxo_ao",
79                          "gcc_disp_gpll0_clk_src",
80                          "gcc_disp_gpll0_div_clk_src",
81                          "dsi0_phy_pll_out_byteclk",
82                          "dsi0_phy_pll_out_dsiclk";
83            #clock-cells = <1>;
84            #reset-cells = <1>;
85            #power-domain-cells = <1>;
86    };
87...
88