1dbb9d53bSLuca Weiss# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2dbb9d53bSLuca Weiss%YAML 1.2 3dbb9d53bSLuca Weiss--- 4dbb9d53bSLuca Weiss$id: http://devicetree.org/schemas/clock/qcom,milos-camcc.yaml# 5dbb9d53bSLuca Weiss$schema: http://devicetree.org/meta-schemas/core.yaml# 6dbb9d53bSLuca Weiss 7dbb9d53bSLuca Weisstitle: Qualcomm Camera Clock & Reset Controller on Milos 8dbb9d53bSLuca Weiss 9dbb9d53bSLuca Weissmaintainers: 10dbb9d53bSLuca Weiss - Luca Weiss <luca.weiss@fairphone.com> 11dbb9d53bSLuca Weiss 12dbb9d53bSLuca Weissdescription: | 13dbb9d53bSLuca Weiss Qualcomm camera clock control module provides the clocks, resets and power 14dbb9d53bSLuca Weiss domains on Milos. 15dbb9d53bSLuca Weiss 16dbb9d53bSLuca Weiss See also: include/dt-bindings/clock/qcom,milos-camcc.h 17dbb9d53bSLuca Weiss 18dbb9d53bSLuca Weissproperties: 19dbb9d53bSLuca Weiss compatible: 20dbb9d53bSLuca Weiss const: qcom,milos-camcc 21dbb9d53bSLuca Weiss 22dbb9d53bSLuca Weiss clocks: 23dbb9d53bSLuca Weiss items: 24dbb9d53bSLuca Weiss - description: Board XO source 25dbb9d53bSLuca Weiss - description: Sleep clock source 26dbb9d53bSLuca Weiss - description: Camera AHB clock from GCC 27dbb9d53bSLuca Weiss 28*7e622e74SLuca Weiss interconnects: 29*7e622e74SLuca Weiss items: 30*7e622e74SLuca Weiss - description: Interconnect path to enable the MultiMedia NoC 31*7e622e74SLuca Weiss 32dbb9d53bSLuca Weissrequired: 33dbb9d53bSLuca Weiss - compatible 34dbb9d53bSLuca Weiss - clocks 35dbb9d53bSLuca Weiss 36dbb9d53bSLuca WeissallOf: 37dbb9d53bSLuca Weiss - $ref: qcom,gcc.yaml# 38dbb9d53bSLuca Weiss 39dbb9d53bSLuca WeissunevaluatedProperties: false 40dbb9d53bSLuca Weiss 41dbb9d53bSLuca Weissexamples: 42dbb9d53bSLuca Weiss - | 43dbb9d53bSLuca Weiss #include <dt-bindings/clock/qcom,milos-gcc.h> 44*7e622e74SLuca Weiss #include <dt-bindings/interconnect/qcom,icc.h> 45*7e622e74SLuca Weiss #include <dt-bindings/interconnect/qcom,milos-rpmh.h> 46dbb9d53bSLuca Weiss clock-controller@adb0000 { 47dbb9d53bSLuca Weiss compatible = "qcom,milos-camcc"; 48dbb9d53bSLuca Weiss reg = <0x0adb0000 0x40000>; 49dbb9d53bSLuca Weiss clocks = <&bi_tcxo_div2>, 50dbb9d53bSLuca Weiss <&sleep_clk>, 51dbb9d53bSLuca Weiss <&gcc GCC_CAMERA_AHB_CLK>; 52*7e622e74SLuca Weiss interconnects = <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 53*7e622e74SLuca Weiss &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ALWAYS>; 54dbb9d53bSLuca Weiss #clock-cells = <1>; 55dbb9d53bSLuca Weiss #reset-cells = <1>; 56dbb9d53bSLuca Weiss #power-domain-cells = <1>; 57dbb9d53bSLuca Weiss }; 58dbb9d53bSLuca Weiss 59dbb9d53bSLuca Weiss... 60