xref: /linux/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml (revision 9f3a2ba62c7226a6604b8aaeb92b5ff906fa4e6b) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on IPQ5332 and IPQ5424
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11
12description: |
13  Qualcomm global clock control module provides the clocks, resets and power
14  domains on IPQ5332 and IPQ5424.
15
16  See also:
17    include/dt-bindings/clock/qcom,gcc-ipq5332.h
18    include/dt-bindings/clock/qcom,gcc-ipq5424.h
19
20properties:
21  compatible:
22    enum:
23      - qcom,ipq5332-gcc
24      - qcom,ipq5424-gcc
25
26  clocks:
27    minItems: 5
28    items:
29      - description: Board XO clock source
30      - description: Sleep clock source
31      - description: PCIE 2lane PHY pipe clock source
32      - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
33      - description: USB PCIE wrapper pipe clock source
34      - description: PCIE 2-lane PHY2 pipe clock source
35      - description: PCIE 2-lane PHY3 pipe clock source
36
37  '#power-domain-cells': false
38  '#interconnect-cells':
39    const: 1
40
41required:
42  - compatible
43  - clocks
44
45allOf:
46  - $ref: qcom,gcc.yaml#
47  - if:
48      properties:
49        compatible:
50          contains:
51            const: qcom,ipq5332-gcc
52    then:
53      properties:
54        clocks:
55          maxItems: 5
56
57  - if:
58      properties:
59        compatible:
60          contains:
61            const: qcom,ipq5424-gcc
62    then:
63      properties:
64        clocks:
65          minItems: 7
66          maxItems: 7
67
68unevaluatedProperties: false
69
70examples:
71  - |
72    clock-controller@1800000 {
73      compatible = "qcom,ipq5332-gcc";
74      reg = <0x01800000 0x80000>;
75      clocks = <&xo_board>,
76               <&sleep_clk>,
77               <&pcie_2lane_phy_pipe_clk>,
78               <&pcie_2lane_phy_pipe_clk_x1>,
79               <&usb_pcie_wrapper_pipe_clk>;
80      #clock-cells = <1>;
81      #reset-cells = <1>;
82    };
83...
84