172a0ca20SVinod Koul# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 272a0ca20SVinod Koul%YAML 1.2 372a0ca20SVinod Koul--- 472a0ca20SVinod Koul$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml# 572a0ca20SVinod Koul$schema: http://devicetree.org/meta-schemas/core.yaml# 672a0ca20SVinod Koul 7ece3c319SKrzysztof Kozlowskititle: Qualcomm Global Clock & Reset Controller on SM8450 872a0ca20SVinod Koul 972a0ca20SVinod Koulmaintainers: 1072a0ca20SVinod Koul - Vinod Koul <vkoul@kernel.org> 1172a0ca20SVinod Koul 1272a0ca20SVinod Kouldescription: | 13ece3c319SKrzysztof Kozlowski Qualcomm global clock control module provides the clocks, resets and power 14ece3c319SKrzysztof Kozlowski domains on SM8450 1572a0ca20SVinod Koul 16ece3c319SKrzysztof Kozlowski See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h 1772a0ca20SVinod Koul 1872a0ca20SVinod Koulproperties: 1972a0ca20SVinod Koul compatible: 2072a0ca20SVinod Koul const: qcom,gcc-sm8450 2172a0ca20SVinod Koul 2272a0ca20SVinod Koul clocks: 2372a0ca20SVinod Koul items: 2472a0ca20SVinod Koul - description: Board XO source 2572a0ca20SVinod Koul - description: Sleep clock source 2672a0ca20SVinod Koul - description: PCIE 0 Pipe clock source (Optional clock) 2772a0ca20SVinod Koul - description: PCIE 1 Pipe clock source (Optional clock) 2847aab533SBjorn Helgaas - description: PCIE 1 Phy Auxiliary clock source (Optional clock) 2972a0ca20SVinod Koul - description: UFS Phy Rx symbol 0 clock source (Optional clock) 3072a0ca20SVinod Koul - description: UFS Phy Rx symbol 1 clock source (Optional clock) 3172a0ca20SVinod Koul - description: UFS Phy Tx symbol 0 clock source (Optional clock) 3272a0ca20SVinod Koul - description: USB3 Phy wrapper pipe clock source (Optional clock) 3372a0ca20SVinod Koul minItems: 2 3472a0ca20SVinod Koul 3572a0ca20SVinod Koul clock-names: 3672a0ca20SVinod Koul items: 3772a0ca20SVinod Koul - const: bi_tcxo 3872a0ca20SVinod Koul - const: sleep_clk 3972a0ca20SVinod Koul - const: pcie_0_pipe_clk # Optional clock 4072a0ca20SVinod Koul - const: pcie_1_pipe_clk # Optional clock 4172a0ca20SVinod Koul - const: pcie_1_phy_aux_clk # Optional clock 4272a0ca20SVinod Koul - const: ufs_phy_rx_symbol_0_clk # Optional clock 4372a0ca20SVinod Koul - const: ufs_phy_rx_symbol_1_clk # Optional clock 4472a0ca20SVinod Koul - const: ufs_phy_tx_symbol_0_clk # Optional clock 4572a0ca20SVinod Koul - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock 4672a0ca20SVinod Koul minItems: 2 4772a0ca20SVinod Koul 4872a0ca20SVinod Koulrequired: 4972a0ca20SVinod Koul - compatible 5072a0ca20SVinod Koul - clocks 5172a0ca20SVinod Koul - clock-names 52*b0ef3434SDmitry Baryshkov - '#power-domain-cells' 5372a0ca20SVinod Koul 540f71ae94SDmitry BaryshkovallOf: 550f71ae94SDmitry Baryshkov - $ref: qcom,gcc.yaml# 560f71ae94SDmitry Baryshkov 570f71ae94SDmitry BaryshkovunevaluatedProperties: false 5872a0ca20SVinod Koul 5972a0ca20SVinod Koulexamples: 6072a0ca20SVinod Koul - | 6172a0ca20SVinod Koul #include <dt-bindings/clock/qcom,rpmh.h> 6272a0ca20SVinod Koul clock-controller@100000 { 6372a0ca20SVinod Koul compatible = "qcom,gcc-sm8450"; 6472a0ca20SVinod Koul reg = <0x00100000 0x001f4200>; 6572a0ca20SVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; 6672a0ca20SVinod Koul clock-names = "bi_tcxo", "sleep_clk"; 6772a0ca20SVinod Koul #clock-cells = <1>; 6872a0ca20SVinod Koul #reset-cells = <1>; 6972a0ca20SVinod Koul #power-domain-cells = <1>; 7072a0ca20SVinod Koul }; 7172a0ca20SVinod Koul 7272a0ca20SVinod Koul... 73