xref: /linux/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml (revision b0ef3434da07e7516a89a80206af53ea81954a80) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on SM8350
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description: |
13  Qualcomm global clock control module provides the clocks, resets and power
14  domains on SM8350.
15
16  See also:: include/dt-bindings/clock/qcom,gcc-sm8350.h
17
18properties:
19  compatible:
20    const: qcom,gcc-sm8350
21
22  clocks:
23    items:
24      - description: Board XO source
25      - description: Sleep clock source
26      - description: PCIE 0 Pipe clock source (Optional clock)
27      - description: PCIE 1 Pipe clock source (Optional clock)
28      - description: UFS card Rx symbol 0 clock source (Optional clock)
29      - description: UFS card Rx symbol 1 clock source (Optional clock)
30      - description: UFS card Tx symbol 0 clock source (Optional clock)
31      - description: UFS phy Rx symbol 0 clock source (Optional clock)
32      - description: UFS phy Rx symbol 1 clock source (Optional clock)
33      - description: UFS phy Tx symbol 0 clock source (Optional clock)
34      - description: USB3 phy wrapper pipe clock source (Optional clock)
35      - description: USB3 phy sec pipe clock source (Optional clock)
36    minItems: 2
37
38  clock-names:
39    items:
40      - const: bi_tcxo
41      - const: sleep_clk
42      - const: pcie_0_pipe_clk # Optional clock
43      - const: pcie_1_pipe_clk # Optional clock
44      - const: ufs_card_rx_symbol_0_clk # Optional clock
45      - const: ufs_card_rx_symbol_1_clk # Optional clock
46      - const: ufs_card_tx_symbol_0_clk # Optional clock
47      - const: ufs_phy_rx_symbol_0_clk # Optional clock
48      - const: ufs_phy_rx_symbol_1_clk # Optional clock
49      - const: ufs_phy_tx_symbol_0_clk # Optional clock
50      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
51      - const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
52    minItems: 2
53
54required:
55  - compatible
56  - clocks
57  - clock-names
58  - '#power-domain-cells'
59
60allOf:
61  - $ref: qcom,gcc.yaml#
62
63unevaluatedProperties: false
64
65examples:
66  - |
67    #include <dt-bindings/clock/qcom,rpmh.h>
68    clock-controller@100000 {
69      compatible = "qcom,gcc-sm8350";
70      reg = <0x00100000 0x1f0000>;
71      clocks = <&rpmhcc RPMH_CXO_CLK>,
72               <&sleep_clk>;
73      clock-names = "bi_tcxo", "sleep_clk";
74      #clock-cells = <1>;
75      #reset-cells = <1>;
76      #power-domain-cells = <1>;
77    };
78
79...
80