xref: /linux/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml (revision a2e8c80845be43607e4957e9d10ec0c05df57a02) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller Binding for SM8350
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description: |
13  Qualcomm global clock control module which supports the clocks, resets and
14  power domains on SM8350.
15
16  See also:
17  - dt-bindings/clock/qcom,gcc-sm8350.h
18
19properties:
20  compatible:
21    const: qcom,gcc-sm8350
22
23  clocks:
24    items:
25      - description: Board XO source
26      - description: Sleep clock source
27      - description: PLL test clock source (Optional clock)
28      - description: PCIE 0 Pipe clock source (Optional clock)
29      - description: PCIE 1 Pipe clock source (Optional clock)
30      - description: UFS card Rx symbol 0 clock source (Optional clock)
31      - description: UFS card Rx symbol 1 clock source (Optional clock)
32      - description: UFS card Tx symbol 0 clock source (Optional clock)
33      - description: UFS phy Rx symbol 0 clock source (Optional clock)
34      - description: UFS phy Rx symbol 1 clock source (Optional clock)
35      - description: UFS phy Tx symbol 0 clock source (Optional clock)
36      - description: USB3 phy wrapper pipe clock source (Optional clock)
37      - description: USB3 phy sec pipe clock source (Optional clock)
38    minItems: 2
39    maxItems: 13
40
41  clock-names:
42    items:
43      - const: bi_tcxo
44      - const: sleep_clk
45      - const: core_bi_pll_test_se # Optional clock
46      - const: pcie_0_pipe_clk # Optional clock
47      - const: pcie_1_pipe_clk # Optional clock
48      - const: ufs_card_rx_symbol_0_clk # Optional clock
49      - const: ufs_card_rx_symbol_1_clk # Optional clock
50      - const: ufs_card_tx_symbol_0_clk # Optional clock
51      - const: ufs_phy_rx_symbol_0_clk # Optional clock
52      - const: ufs_phy_rx_symbol_1_clk # Optional clock
53      - const: ufs_phy_tx_symbol_0_clk # Optional clock
54      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
55      - const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
56    minItems: 2
57    maxItems: 13
58
59  '#clock-cells':
60    const: 1
61
62  '#reset-cells':
63    const: 1
64
65  '#power-domain-cells':
66    const: 1
67
68  reg:
69    maxItems: 1
70
71required:
72  - compatible
73  - clocks
74  - clock-names
75  - reg
76  - '#clock-cells'
77  - '#reset-cells'
78  - '#power-domain-cells'
79
80additionalProperties: false
81
82examples:
83  - |
84    #include <dt-bindings/clock/qcom,rpmh.h>
85    clock-controller@100000 {
86      compatible = "qcom,gcc-sm8350";
87      reg = <0x00100000 0x1f0000>;
88      clocks = <&rpmhcc RPMH_CXO_CLK>,
89               <&sleep_clk>;
90      clock-names = "bi_tcxo", "sleep_clk";
91      #clock-cells = <1>;
92      #reset-cells = <1>;
93      #power-domain-cells = <1>;
94    };
95
96...
97