1*44fad332SAlban BedelBinding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller 2*44fad332SAlban Bedel 3*44fad332SAlban BedelThe PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB. 4*44fad332SAlban Bedel 5*44fad332SAlban BedelRequired Properties: 6*44fad332SAlban Bedel- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following 7*44fad332SAlban Bedel fallbacks: 8*44fad332SAlban Bedel - "qca,ar7100-pll" 9*44fad332SAlban Bedel - "qca,ar7240-pll" 10*44fad332SAlban Bedel - "qca,ar9130-pll" 11*44fad332SAlban Bedel - "qca,ar9330-pll" 12*44fad332SAlban Bedel - "qca,ar9340-pll" 13*44fad332SAlban Bedel - "qca,qca9550-pll" 14*44fad332SAlban Bedel- reg: Base address and size of the controllers memory area 15*44fad332SAlban Bedel- clock-names: Name of the input clock, has to be "ref" 16*44fad332SAlban Bedel- clocks: phandle of the external reference clock 17*44fad332SAlban Bedel- #clock-cells: has to be one 18*44fad332SAlban Bedel 19*44fad332SAlban BedelOptional properties: 20*44fad332SAlban Bedel- clock-output-names: should be "cpu", "ddr", "ahb" 21*44fad332SAlban Bedel 22*44fad332SAlban BedelExample: 23*44fad332SAlban Bedel 24*44fad332SAlban Bedel memory-controller@18050000 { 25*44fad332SAlban Bedel compatible = "qca,ar9132-ppl", "qca,ar9130-pll"; 26*44fad332SAlban Bedel reg = <0x18050000 0x20>; 27*44fad332SAlban Bedel 28*44fad332SAlban Bedel clock-names = "ref"; 29*44fad332SAlban Bedel clocks = <&extosc>; 30*44fad332SAlban Bedel 31*44fad332SAlban Bedel #clock-cells = <1>; 32*44fad332SAlban Bedel clock-output-names = "cpu", "ddr", "ahb"; 33*44fad332SAlban Bedel }; 34