144fad332SAlban BedelBinding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller 244fad332SAlban Bedel 344fad332SAlban BedelThe PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB. 444fad332SAlban Bedel 544fad332SAlban BedelRequired Properties: 6*2b885ea6SAntony Pavlov- compatible: has to be "qca,<soctype>-pll" and one of the following 744fad332SAlban Bedel fallbacks: 844fad332SAlban Bedel - "qca,ar7100-pll" 944fad332SAlban Bedel - "qca,ar7240-pll" 1044fad332SAlban Bedel - "qca,ar9130-pll" 1144fad332SAlban Bedel - "qca,ar9330-pll" 1244fad332SAlban Bedel - "qca,ar9340-pll" 1344fad332SAlban Bedel - "qca,qca9550-pll" 1444fad332SAlban Bedel- reg: Base address and size of the controllers memory area 1544fad332SAlban Bedel- clock-names: Name of the input clock, has to be "ref" 1644fad332SAlban Bedel- clocks: phandle of the external reference clock 1744fad332SAlban Bedel- #clock-cells: has to be one 1844fad332SAlban Bedel 1944fad332SAlban BedelOptional properties: 2044fad332SAlban Bedel- clock-output-names: should be "cpu", "ddr", "ahb" 2144fad332SAlban Bedel 2244fad332SAlban BedelExample: 2344fad332SAlban Bedel 24*2b885ea6SAntony Pavlov pll-controller@18050000 { 25*2b885ea6SAntony Pavlov compatible = "qca,ar9132-pll", "qca,ar9130-pll"; 2644fad332SAlban Bedel reg = <0x18050000 0x20>; 2744fad332SAlban Bedel 2844fad332SAlban Bedel clock-names = "ref"; 2944fad332SAlban Bedel clocks = <&extosc>; 3044fad332SAlban Bedel 3144fad332SAlban Bedel #clock-cells = <1>; 3244fad332SAlban Bedel clock-output-names = "cpu", "ddr", "ahb"; 3344fad332SAlban Bedel }; 34