xref: /linux/Documentation/devicetree/bindings/clock/nxp,imx95-display-master-csr.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/nxp,imx95-display-master-csr.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP i.MX95 Display Master Block Control
8
9maintainers:
10  - Peng Fan <peng.fan@nxp.com>
11
12properties:
13  compatible:
14    items:
15      - const: nxp,imx95-display-master-csr
16      - const: syscon
17
18  reg:
19    maxItems: 1
20
21  power-domains:
22    maxItems: 1
23
24  clocks:
25    maxItems: 1
26
27  '#clock-cells':
28    const: 1
29    description:
30      The clock consumer should specify the desired clock by having the clock
31      ID in its "clocks" phandle cell. See
32      include/dt-bindings/clock/nxp,imx95-clock.h
33
34  mux-controller:
35    type: object
36    $ref: /schemas/mux/reg-mux.yaml
37
38required:
39  - compatible
40  - reg
41  - '#clock-cells'
42  - mux-controller
43  - power-domains
44  - clocks
45
46additionalProperties: false
47
48examples:
49  - |
50    syscon@4c410000 {
51      compatible = "nxp,imx95-display-master-csr", "syscon";
52      reg = <0x4c410000 0x10000>;
53      #clock-cells = <1>;
54      clocks = <&scmi_clk 62>;
55      power-domains = <&scmi_devpd 3>;
56
57      mux: mux-controller {
58        compatible = "mmio-mux";
59        #mux-control-cells = <1>;
60        mux-reg-masks = <0x4 0x00000001>; /* Pixel_link_sel */
61        idle-states = <0>;
62      };
63    };
64...
65