xref: /linux/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml (revision 39f75da7bcc829ddc4d40bb60d0e95520de7898b) 
1# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra Clock and Reset Controller
8
9maintainers:
10  - Jon Hunter <jonathanh@nvidia.com>
11  - Thierry Reding <thierry.reding@gmail.com>
12
13description: |
14  The Clock and Reset (CAR) is the HW module responsible for muxing and gating
15  Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
16
17  CLKGEN provides the registers to program the PLLs. It controls most of
18  the clock source programming and most of the clock dividers.
19
20  CLKGEN input signals include the external clock for the reference frequency
21  (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
22
23  Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
24
25  RSTGEN provides the registers needed to control resetting of each block in
26  the Tegra system.
27
28properties:
29  compatible:
30    const: nvidia,tegra124-car
31
32  reg:
33    maxItems: 1
34
35  '#clock-cells':
36    const: 1
37
38  "#reset-cells":
39    const: 1
40
41  nvidia,external-memory-controller:
42    $ref: /schemas/types.yaml#/definitions/phandle
43    description:
44      phandle of the external memory controller node
45
46patternProperties:
47  "^emc-timings-[0-9]+$":
48    type: object
49    properties:
50      nvidia,ram-code:
51        $ref: /schemas/types.yaml#/definitions/uint32
52        description:
53          value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
54          this timing set is used for
55
56    patternProperties:
57      "^timing-[0-9]+$":
58        type: object
59        properties:
60          clock-frequency:
61            description:
62              external memory clock rate in Hz
63            minimum: 1000000
64            maximum: 1000000000
65
66          nvidia,parent-clock-frequency:
67            $ref: /schemas/types.yaml#/definitions/uint32
68            description:
69              rate of parent clock in Hz
70            minimum: 1000000
71            maximum: 1000000000
72
73          clocks:
74            items:
75              - description: parent clock of EMC
76
77          clock-names:
78            items:
79              - const: emc-parent
80
81        required:
82          - clock-frequency
83          - nvidia,parent-clock-frequency
84          - clocks
85          - clock-names
86
87        additionalProperties: false
88
89    additionalProperties: false
90
91required:
92  - compatible
93  - reg
94  - '#clock-cells'
95  - "#reset-cells"
96
97additionalProperties: false
98
99examples:
100  - |
101    #include <dt-bindings/clock/tegra124-car.h>
102
103    car: clock-controller@60006000 {
104        compatible = "nvidia,tegra124-car";
105        reg = <0x60006000 0x1000>;
106        #clock-cells = <1>;
107        #reset-cells = <1>;
108    };
109
110    usb-controller@c5004000 {
111        compatible = "nvidia,tegra20-ehci";
112        reg = <0xc5004000 0x4000>;
113        clocks = <&car TEGRA124_CLK_USB2>;
114        resets = <&car TEGRA124_CLK_USB2>;
115    };
116