xref: /linux/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml (revision d30c1683aaecb93d2ab95685dc4300a33d3cea7a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip PolarFire Clock Control Module
8
9maintainers:
10  - Daire McNamara <daire.mcnamara@microchip.com>
11
12description: |
13  Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
14  which gates and enables all peripheral clocks.
15
16  This device tree binding describes 33 gate clocks.  Clocks are referenced by
17  user nodes by the CLKCFG node phandle and the clock index in the group, from
18  0 to 32.
19
20properties:
21  compatible:
22    const: microchip,mpfs-clkcfg
23
24  reg:
25    oneOf:
26      - items:
27          - description: |
28              clock config registers:
29              These registers contain enable, reset & divider tables for the, cpu,
30              axi, ahb and rtc/mtimer reference clocks as well as enable and reset
31              for the peripheral clocks.
32          - description: |
33              mss pll dri registers:
34              Block of registers responsible for dynamic reconfiguration of the mss
35              pll
36        deprecated: true
37      - items:
38          - description: |
39              mss pll dri registers:
40              Block of registers responsible for dynamic reconfiguration of the mss
41              pll
42
43  clocks:
44    maxItems: 1
45
46  '#clock-cells':
47    const: 1
48    description: |
49      The clock consumer should specify the desired clock by having the clock
50      ID in its "clocks" phandle cell.
51      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
52      PolarFire clock IDs.
53
54  resets:
55    maxItems: 1
56
57  '#reset-cells':
58    description:
59      The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
60      CLK_ENVM to CLK_CFM. The reset consumer should specify the desired
61      peripheral via the clock ID in its "resets" phandle cell.
62      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
63      PolarFire clock IDs.
64    const: 1
65
66required:
67  - compatible
68  - reg
69  - clocks
70  - '#clock-cells'
71
72additionalProperties: false
73
74examples:
75  # Clock Config node:
76  - |
77    #include <dt-bindings/clock/microchip,mpfs-clock.h>
78    soc {
79            #address-cells = <1>;
80            #size-cells = <1>;
81
82            clkcfg: clock-controller@3E001000 {
83                compatible = "microchip,mpfs-clkcfg";
84                reg = <0x3E001000 0x1000>;
85                clocks = <&ref>;
86                #clock-cells = <1>;
87        };
88    };
89