xref: /linux/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml (revision be1ca3ee8f97067fee87fda73ea5959d5ab75bbf) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip PolarFire Clock Control Module
8
9maintainers:
10  - Daire McNamara <daire.mcnamara@microchip.com>
11
12description: |
13  Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
14  which gates and enables all peripheral clocks.
15
16  This device tree binding describes 33 gate clocks.  Clocks are referenced by
17  user nodes by the CLKCFG node phandle and the clock index in the group, from
18  0 to 32.
19
20properties:
21  compatible:
22    oneOf:
23      - items:
24          - const: microchip,pic64gx-clkcfg
25          - const: microchip,mpfs-clkcfg
26      - const: microchip,mpfs-clkcfg
27
28  reg:
29    oneOf:
30      - items:
31          - description: |
32              clock config registers:
33              These registers contain enable, reset & divider tables for the, cpu,
34              axi, ahb and rtc/mtimer reference clocks as well as enable and reset
35              for the peripheral clocks.
36          - description: |
37              mss pll dri registers:
38              Block of registers responsible for dynamic reconfiguration of the mss
39              pll
40        deprecated: true
41      - items:
42          - description: |
43              mss pll dri registers:
44              Block of registers responsible for dynamic reconfiguration of the mss
45              pll
46
47  clocks:
48    maxItems: 1
49
50  '#clock-cells':
51    const: 1
52    description: |
53      The clock consumer should specify the desired clock by having the clock
54      ID in its "clocks" phandle cell.
55      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
56      PolarFire clock IDs.
57
58  resets:
59    maxItems: 1
60
61  '#reset-cells':
62    description:
63      The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
64      CLK_ENVM to CLK_CFM. The reset consumer should specify the desired
65      peripheral via the clock ID in its "resets" phandle cell.
66      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
67      PolarFire clock IDs.
68    const: 1
69
70required:
71  - compatible
72  - reg
73  - clocks
74  - '#clock-cells'
75
76if:
77  properties:
78    compatible:
79      contains:
80        const: microchip,pic64gx-clkcfg
81then:
82  properties:
83    reg:
84      maxItems: 1
85
86additionalProperties: false
87
88examples:
89  # Clock Config node:
90  - |
91    #include <dt-bindings/clock/microchip,mpfs-clock.h>
92    soc {
93            #address-cells = <1>;
94            #size-cells = <1>;
95
96            clkcfg: clock-controller@3E001000 {
97                compatible = "microchip,mpfs-clkcfg";
98                reg = <0x3E001000 0x1000>;
99                clocks = <&ref>;
100                #clock-cells = <1>;
101        };
102    };
103