xref: /linux/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip LAN966X Generic Clock Controller
8
9maintainers:
10  - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
11
12description: |
13  The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
14  ddr_clk and sys_clk. This clock controller generates and supplies
15  clock to various peripherals within the SoC.
16
17properties:
18  compatible:
19    oneOf:
20      - enum:
21          - microchip,lan966x-gck
22          - microchip,lan9691-gck
23      - items:
24          - enum:
25              - microchip,lan9698-gck
26              - microchip,lan9696-gck
27              - microchip,lan9694-gck
28              - microchip,lan9693-gck
29              - microchip,lan9692-gck
30          - const: microchip,lan9691-gck
31
32  reg:
33    minItems: 1
34    items:
35      - description: Generic clock registers
36      - description: Optional gate clock registers
37
38  clocks:
39    items:
40      - description: CPU clock source
41      - description: DDR clock source
42      - description: System clock source
43
44  clock-names:
45    items:
46      - const: cpu
47      - const: ddr
48      - const: sys
49
50  '#clock-cells':
51    const: 1
52
53required:
54  - compatible
55  - reg
56  - clocks
57  - clock-names
58  - '#clock-cells'
59
60additionalProperties: false
61
62examples:
63  - |
64    clks: clock-controller@e00c00a8 {
65        compatible = "microchip,lan966x-gck";
66        #clock-cells = <1>;
67        clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
68        clock-names = "cpu", "ddr", "sys";
69        reg = <0xe00c00a8 0x38>;
70    };
71...
72