xref: /linux/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml (revision beaea9c4ba2d8ef1b10223dc3a75a7d7be3e5cd9) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MTMIPS SoCs System Controller
8
9maintainers:
10  - Sergio Paracuellos <sergio.paracuellos@gmail.com>
11
12description: |
13  MediaTek MIPS and Ralink SoCs provides a system controller to allow
14  to access to system control registers. These registers include clock
15  and reset related ones so this node is both clock and reset provider
16  for the rest of the world.
17
18  These SoCs have an XTAL from where the cpu clock is
19  provided as well as derived clocks for the bus and the peripherals.
20
21  Each clock is assigned an identifier and client nodes use this identifier
22  to specify the clock which they consume.
23
24  All these identifiers could be found in:
25  [1]: <include/dt-bindings/clock/mediatek,mtmips-sysc.h>.
26
27properties:
28  compatible:
29    oneOf:
30      - items:
31          - enum:
32              - ralink,mt7620-sysc
33              - ralink,mt7688-sysc
34              - ralink,rt2880-sysc
35              - ralink,rt3050-sysc
36              - ralink,rt3052-sysc
37              - ralink,rt3352-sysc
38              - ralink,rt3883-sysc
39              - ralink,rt5350-sysc
40          - const: syscon
41      - items:
42          - const: ralink,mt7628-sysc
43          - const: ralink,mt7688-sysc
44          - const: syscon
45
46  reg:
47    maxItems: 1
48
49  '#clock-cells':
50    description:
51      The first cell indicates the clock number, see [1] for available
52      clocks.
53    const: 1
54
55  '#reset-cells':
56    description:
57      The first cell indicates the reset bit within the register.
58    const: 1
59
60required:
61  - compatible
62  - reg
63  - '#clock-cells'
64  - '#reset-cells'
65
66additionalProperties: false
67
68examples:
69  - |
70    #include <dt-bindings/clock/mediatek,mtmips-sysc.h>
71
72    syscon@0 {
73      compatible = "ralink,rt5350-sysc", "syscon";
74      reg = <0x0 0x100>;
75      #clock-cells = <1>;
76      #reset-cells = <1>;
77    };
78