xref: /linux/Documentation/devicetree/bindings/clock/mediatek,mt8365-sys-clock.yaml (revision 00e07cfbdf0b232f7553f0175f8f4e8d792f7e90) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/mediatek,mt8365-sys-clock.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek System Clock Controller for MT8365
8
9maintainers:
10  - Markus Schneider-Pargmann <msp@baylibre.com>
11
12description:
13  The apmixedsys module provides most of PLLs which generated from SoC 26m.
14  The topckgen provides dividers and muxes which provides the clock source to other IP blocks.
15  The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
16
17properties:
18  compatible:
19    items:
20      - enum:
21          - mediatek,mt8365-topckgen
22          - mediatek,mt8365-infracfg
23          - mediatek,mt8365-apmixedsys
24          - mediatek,mt8365-pericfg
25          - mediatek,mt8365-mcucfg
26      - const: syscon
27
28  reg:
29    maxItems: 1
30
31  '#clock-cells':
32    const: 1
33
34required:
35  - compatible
36  - reg
37  - '#clock-cells'
38
39additionalProperties: false
40
41examples:
42  - |
43    topckgen: clock-controller@10000000 {
44        compatible = "mediatek,mt8365-topckgen", "syscon";
45        reg = <0x10000000 0x1000>;
46        #clock-cells = <1>;
47    };
48