xref: /linux/Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml (revision 522ba450b56fff29f868b1552bdc2965f55de7ed)

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Functional Clock Controller for MT8196

maintainers:
  - Guangjie Song <guangjie.song@mediatek.com>
  - Laura Nao <laura.nao@collabora.com>

description: |
  The clock architecture in MediaTek SoCs is structured like below:
  PLLs -->
          dividers -->
                      muxes
                           -->
                              clock gate

  The device nodes provide clock gate control in different IP blocks.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8196-imp-iic-wrap-c
          - mediatek,mt8196-imp-iic-wrap-e
          - mediatek,mt8196-imp-iic-wrap-n
          - mediatek,mt8196-imp-iic-wrap-w
          - mediatek,mt8196-mdpsys0
          - mediatek,mt8196-mdpsys1
          - mediatek,mt8196-pericfg-ao
          - mediatek,mt8196-pextp0cfg-ao
          - mediatek,mt8196-pextp1cfg-ao
          - mediatek,mt8196-ufscfg-ao
          - mediatek,mt8196-vencsys
          - mediatek,mt8196-vencsys-c1
          - mediatek,mt8196-vencsys-c2
          - mediatek,mt8196-vdecsys
          - mediatek,mt8196-vdecsys-soc
          - mediatek,mt8196-vdisp-ao
      - const: syscon

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1
    description:
      Reset lines for PEXTP0/1 and UFS blocks.

  mediatek,hardware-voter:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      Phandle to the "Hardware Voter" (HWV), as named in the vendor
      documentation for MT8196/MT6991.

      The HWV is a SoC-internal fixed-function MCU used to collect votes from
      both the Application Processor and other remote processors within the SoC.
      It is intended to transparently enable or disable hardware resources (such
      as power domains or clocks) based on internal vote aggregation handled by
      the MCU's internal state machine.

      However, in practice, this design is incomplete. While the HWV performs
      some internal vote aggregation,software is still required to
      - Manually enable power supplies externally, if present and if required
      - Manually enable parent clocks via direct MMIO writes to clock controllers
      - Enable the FENC after the clock has been ungated via direct MMIO
      writes to clock controllers

      As such, the HWV behaves more like a hardware-managed clock reference
      counter than a true voter. Furthermore, it is not a separate
      controller. It merely serves as an alternative interface to the same
      underlying clock or power controller. Actual control still requires
      direct access to the controller's own MMIO register space, in
      addition to writing to the HWV's MMIO region.

      For this reason, a custom phandle is used here - drivers need to directly
      access the HWV MMIO region in a syscon-like fashion, due to how the
      hardware is wired. This differs from true hardware voting systems, which
      typically do not require custom phandles and rely instead on generic APIs
      (clocks, power domains, interconnects).

      The name "hardware-voter" is retained to match vendor documentation, but
      this should not be reused or misunderstood as a proper voting mechanism.

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    pericfg_ao: clock-controller@16640000 {
        compatible = "mediatek,mt8196-pericfg-ao", "syscon";
        reg = <0x16640000 0x1000>;
        mediatek,hardware-voter = <&scp_hwv>;
        #clock-cells = <1>;
    };
  - |
    pextp0cfg_ao: clock-controller@169b0000 {
        compatible = "mediatek,mt8196-pextp0cfg-ao", "syscon";
        reg = <0x169b0000 0x1000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
    };