xref: /linux/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml (revision 34dc1baba215b826e454b8d19e4f24adbeb7d00d) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek System Clock Controller for MT8188
8
9maintainers:
10  - Garmin Chang <garmin.chang@mediatek.com>
11
12description: |
13  The clock architecture in MediaTek like below
14  PLLs -->
15          dividers -->
16                      muxes
17                           -->
18                              clock gate
19
20  The apmixedsys provides most of PLLs which generated from SoC 26m.
21  The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
22  The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
23  The mcusys provides mux control to select the clock source in AP MCU.
24  The device nodes also provide the system control capacity for configuration.
25
26properties:
27  compatible:
28    items:
29      - enum:
30          - mediatek,mt8188-apmixedsys
31          - mediatek,mt8188-infracfg-ao
32          - mediatek,mt8188-pericfg-ao
33          - mediatek,mt8188-topckgen
34      - const: syscon
35
36  reg:
37    maxItems: 1
38
39  '#clock-cells':
40    const: 1
41
42required:
43  - compatible
44  - reg
45  - '#clock-cells'
46
47additionalProperties: false
48
49examples:
50  - |
51    clock-controller@10000000 {
52        compatible = "mediatek,mt8188-topckgen", "syscon";
53        reg = <0x10000000 0x1000>;
54        #clock-cells = <1>;
55    };
56