xref: /linux/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml (revision be239684b18e1cdcafcf8c7face4a2f562c745ad) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Functional Clock Controller for MT8188
8
9maintainers:
10  - Garmin Chang <garmin.chang@mediatek.com>
11
12description: |
13  The clock architecture in MediaTek like below
14  PLLs -->
15          dividers -->
16                      muxes
17                           -->
18                              clock gate
19
20  The devices provide clock gate control in different IP blocks.
21
22properties:
23  compatible:
24    enum:
25      - mediatek,mt8188-adsp-audio26m
26      - mediatek,mt8188-camsys
27      - mediatek,mt8188-camsys-rawa
28      - mediatek,mt8188-camsys-rawb
29      - mediatek,mt8188-camsys-yuva
30      - mediatek,mt8188-camsys-yuvb
31      - mediatek,mt8188-ccusys
32      - mediatek,mt8188-imgsys
33      - mediatek,mt8188-imgsys-wpe1
34      - mediatek,mt8188-imgsys-wpe2
35      - mediatek,mt8188-imgsys-wpe3
36      - mediatek,mt8188-imgsys1-dip-nr
37      - mediatek,mt8188-imgsys1-dip-top
38      - mediatek,mt8188-imp-iic-wrap-c
39      - mediatek,mt8188-imp-iic-wrap-en
40      - mediatek,mt8188-imp-iic-wrap-w
41      - mediatek,mt8188-ipesys
42      - mediatek,mt8188-mfgcfg
43      - mediatek,mt8188-vdecsys
44      - mediatek,mt8188-vdecsys-soc
45      - mediatek,mt8188-vencsys
46      - mediatek,mt8188-wpesys
47      - mediatek,mt8188-wpesys-vpp0
48
49  reg:
50    maxItems: 1
51
52  '#clock-cells':
53    const: 1
54
55required:
56  - compatible
57  - reg
58  - '#clock-cells'
59
60additionalProperties: false
61
62examples:
63  - |
64    clock-controller@11283000 {
65        compatible = "mediatek,mt8188-imp-iic-wrap-c";
66        reg = <0x11283000 0x1000>;
67        #clock-cells = <1>;
68    };
69
70