xref: /linux/Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/mediatek,mt7622-pciesys.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek PCIESYS clock and reset controller
8
9description:
10  The MediaTek PCIESYS controller provides various clocks to the system.
11
12maintainers:
13  - Matthias Brugger <matthias.bgg@gmail.com>
14
15properties:
16  compatible:
17    oneOf:
18      - items:
19          - const: mediatek,mt7622-pciesys
20          - const: syscon
21      - const: mediatek,mt7629-pciesys
22
23  reg:
24    maxItems: 1
25
26  "#clock-cells":
27    const: 1
28    description: The available clocks are defined in dt-bindings/clock/mt*-clk.h
29
30  "#reset-cells":
31    const: 1
32
33required:
34  - reg
35  - "#clock-cells"
36  - "#reset-cells"
37
38additionalProperties: false
39
40examples:
41  - |
42    clock-controller@1a100800 {
43        compatible = "mediatek,mt7622-pciesys", "syscon";
44        reg = <0x1a100800 0x1000>;
45        #clock-cells = <1>;
46        #reset-cells = <1>;
47    };
48