xref: /linux/Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml (revision 1f20a5769446a1acae67ac9e63d07a594829a789) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/mediatek,mt7622-pciesys.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek PCIESYS clock and reset controller
8
9description:
10  The MediaTek PCIESYS controller provides various clocks to the system.
11
12maintainers:
13  - Matthias Brugger <matthias.bgg@gmail.com>
14
15properties:
16  compatible:
17    enum:
18      - mediatek,mt7622-pciesys
19      - mediatek,mt7629-pciesys
20
21  reg:
22    maxItems: 1
23
24  "#clock-cells":
25    const: 1
26    description: The available clocks are defined in dt-bindings/clock/mt*-clk.h
27
28  "#reset-cells":
29    const: 1
30
31required:
32  - reg
33  - "#clock-cells"
34  - "#reset-cells"
35
36additionalProperties: false
37
38examples:
39  - |
40    clock-controller@1a100800 {
41        compatible = "mediatek,mt7622-pciesys";
42        reg = <0x1a100800 0x1000>;
43        #clock-cells = <1>;
44        #reset-cells = <1>;
45    };
46