xref: /linux/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml (revision 79d2e1919a2728ef49d938eb20ebd5903c14dfb0) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/mediatek,infracfg.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Infrastructure System Configuration Controller
8
9maintainers:
10  - Matthias Brugger <matthias.bgg@gmail.com>
11
12description:
13  The Mediatek infracfg controller provides various clocks and reset outputs
14  to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>
15  and <dt-bindings/clock/mediatek,mt*-infracfg.h>, and reset values in
16  <dt-bindings/reset/mt*-reset.h>, <dt-bindings/reset/mt*-resets.h> and
17  <dt-bindings/reset/mediatek,mt*-infracfg.h>.
18
19properties:
20  compatible:
21    oneOf:
22      - items:
23          - enum:
24              - mediatek,mt2701-infracfg
25              - mediatek,mt2712-infracfg
26              - mediatek,mt6735-infracfg
27              - mediatek,mt6765-infracfg
28              - mediatek,mt6795-infracfg
29              - mediatek,mt6779-infracfg_ao
30              - mediatek,mt6797-infracfg
31              - mediatek,mt7622-infracfg
32              - mediatek,mt7629-infracfg
33              - mediatek,mt7981-infracfg
34              - mediatek,mt7986-infracfg
35              - mediatek,mt7988-infracfg
36              - mediatek,mt8135-infracfg
37              - mediatek,mt8167-infracfg
38              - mediatek,mt8173-infracfg
39              - mediatek,mt8183-infracfg
40              - mediatek,mt8516-infracfg
41          - const: syscon
42      - items:
43          - const: mediatek,mt7623-infracfg
44          - const: mediatek,mt2701-infracfg
45          - const: syscon
46
47  reg:
48    maxItems: 1
49
50  '#clock-cells':
51    const: 1
52
53  '#reset-cells':
54    const: 1
55
56required:
57  - compatible
58  - reg
59  - '#clock-cells'
60
61if:
62  properties:
63    compatible:
64      contains:
65        enum:
66          - mediatek,mt2701-infracfg
67          - mediatek,mt2712-infracfg
68          - mediatek,mt6795-infracfg
69          - mediatek,mt7622-infracfg
70          - mediatek,mt7986-infracfg
71          - mediatek,mt8135-infracfg
72          - mediatek,mt8173-infracfg
73          - mediatek,mt8183-infracfg
74then:
75  required:
76    - '#reset-cells'
77
78additionalProperties: false
79
80examples:
81  - |
82    infracfg: clock-controller@10001000 {
83        compatible = "mediatek,mt8173-infracfg", "syscon";
84        reg = <0x10001000 0x1000>;
85        #clock-cells = <1>;
86        #reset-cells = <1>;
87    };
88