xref: /linux/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml (revision cd9fdd06b0e8aafc715f239153ff41cbf12c991a)
1*cd9fdd06SYassine Oudjana# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*cd9fdd06SYassine Oudjana%YAML 1.2
3*cd9fdd06SYassine Oudjana---
4*cd9fdd06SYassine Oudjana$id: "http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#"
5*cd9fdd06SYassine Oudjana$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6*cd9fdd06SYassine Oudjana
7*cd9fdd06SYassine Oudjanatitle: MediaTek Top Clock Generator Controller
8*cd9fdd06SYassine Oudjana
9*cd9fdd06SYassine Oudjanamaintainers:
10*cd9fdd06SYassine Oudjana  - Michael Turquette <mturquette@baylibre.com>
11*cd9fdd06SYassine Oudjana  - Stephen Boyd <sboyd@kernel.org>
12*cd9fdd06SYassine Oudjana
13*cd9fdd06SYassine Oudjanadescription:
14*cd9fdd06SYassine Oudjana  The Mediatek topckgen controller provides various clocks to the system.
15*cd9fdd06SYassine Oudjana  The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
16*cd9fdd06SYassine Oudjana
17*cd9fdd06SYassine Oudjanaproperties:
18*cd9fdd06SYassine Oudjana  compatible:
19*cd9fdd06SYassine Oudjana    oneOf:
20*cd9fdd06SYassine Oudjana      - enum:
21*cd9fdd06SYassine Oudjana          - mediatek,mt6797-topckgen
22*cd9fdd06SYassine Oudjana          - mediatek,mt7622-topckgen
23*cd9fdd06SYassine Oudjana          - mediatek,mt8135-topckgen
24*cd9fdd06SYassine Oudjana          - mediatek,mt8173-topckgen
25*cd9fdd06SYassine Oudjana          - mediatek,mt8516-topckgen
26*cd9fdd06SYassine Oudjana      - items:
27*cd9fdd06SYassine Oudjana          - const: mediatek,mt7623-topckgen
28*cd9fdd06SYassine Oudjana          - const: mediatek,mt2701-topckgen
29*cd9fdd06SYassine Oudjana          - const: syscon
30*cd9fdd06SYassine Oudjana      - items:
31*cd9fdd06SYassine Oudjana          - enum:
32*cd9fdd06SYassine Oudjana              - mediatek,mt2701-topckgen
33*cd9fdd06SYassine Oudjana              - mediatek,mt2712-topckgen
34*cd9fdd06SYassine Oudjana              - mediatek,mt6765-topckgen
35*cd9fdd06SYassine Oudjana              - mediatek,mt6779-topckgen
36*cd9fdd06SYassine Oudjana              - mediatek,mt7629-topckgen
37*cd9fdd06SYassine Oudjana              - mediatek,mt7986-topckgen
38*cd9fdd06SYassine Oudjana              - mediatek,mt8167-topckgen
39*cd9fdd06SYassine Oudjana              - mediatek,mt8183-topckgen
40*cd9fdd06SYassine Oudjana          - const: syscon
41*cd9fdd06SYassine Oudjana
42*cd9fdd06SYassine Oudjana  reg:
43*cd9fdd06SYassine Oudjana    maxItems: 1
44*cd9fdd06SYassine Oudjana
45*cd9fdd06SYassine Oudjana  '#clock-cells':
46*cd9fdd06SYassine Oudjana    const: 1
47*cd9fdd06SYassine Oudjana
48*cd9fdd06SYassine Oudjanarequired:
49*cd9fdd06SYassine Oudjana  - compatible
50*cd9fdd06SYassine Oudjana  - reg
51*cd9fdd06SYassine Oudjana  - '#clock-cells'
52*cd9fdd06SYassine Oudjana
53*cd9fdd06SYassine OudjanaadditionalProperties: false
54*cd9fdd06SYassine Oudjana
55*cd9fdd06SYassine Oudjanaexamples:
56*cd9fdd06SYassine Oudjana  - |
57*cd9fdd06SYassine Oudjana    topckgen: clock-controller@10000000 {
58*cd9fdd06SYassine Oudjana        compatible = "mediatek,mt8173-topckgen";
59*cd9fdd06SYassine Oudjana        reg = <0x10000000 0x1000>;
60*cd9fdd06SYassine Oudjana        #clock-cells = <1>;
61*cd9fdd06SYassine Oudjana    };
62