xref: /linux/Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.yaml (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/mediatek,mt8195-clock.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Functional Clock Controller for MT8195
8
9maintainers:
10  - Chun-Jie Chen <chun-jie.chen@mediatek.com>
11
12description:
13  The clock architecture in Mediatek like below
14  PLLs -->
15          dividers -->
16                      muxes
17                           -->
18                              clock gate
19
20  The devices except apusys_pll provide clock gate control in different IP blocks.
21  The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
22
23properties:
24  compatible:
25    items:
26      - enum:
27          - mediatek,mt8195-scp_adsp
28          - mediatek,mt8195-imp_iic_wrap_s
29          - mediatek,mt8195-imp_iic_wrap_w
30          - mediatek,mt8195-mfgcfg
31          - mediatek,mt8195-wpesys
32          - mediatek,mt8195-wpesys_vpp0
33          - mediatek,mt8195-wpesys_vpp1
34          - mediatek,mt8195-imgsys
35          - mediatek,mt8195-imgsys1_dip_top
36          - mediatek,mt8195-imgsys1_dip_nr
37          - mediatek,mt8195-imgsys1_wpe
38          - mediatek,mt8195-ipesys
39          - mediatek,mt8195-camsys
40          - mediatek,mt8195-camsys_rawa
41          - mediatek,mt8195-camsys_yuva
42          - mediatek,mt8195-camsys_rawb
43          - mediatek,mt8195-camsys_yuvb
44          - mediatek,mt8195-camsys_mraw
45          - mediatek,mt8195-ccusys
46          - mediatek,mt8195-vdecsys_soc
47          - mediatek,mt8195-vdecsys
48          - mediatek,mt8195-vdecsys_core1
49          - mediatek,mt8195-vencsys
50          - mediatek,mt8195-vencsys_core1
51          - mediatek,mt8195-apusys_pll
52  reg:
53    maxItems: 1
54
55  '#clock-cells':
56    const: 1
57
58required:
59  - compatible
60  - reg
61
62additionalProperties: false
63
64examples:
65  - |
66    scp_adsp: clock-controller@10720000 {
67        compatible = "mediatek,mt8195-scp_adsp";
68        reg = <0x10720000 0x1000>;
69        #clock-cells = <1>;
70    };
71
72  - |
73    imp_iic_wrap_s: clock-controller@11d03000 {
74        compatible = "mediatek,mt8195-imp_iic_wrap_s";
75        reg = <0x11d03000 0x1000>;
76        #clock-cells = <1>;
77    };
78
79  - |
80    imp_iic_wrap_w: clock-controller@11e05000 {
81        compatible = "mediatek,mt8195-imp_iic_wrap_w";
82        reg = <0x11e05000 0x1000>;
83        #clock-cells = <1>;
84    };
85
86  - |
87    mfgcfg: clock-controller@13fbf000 {
88        compatible = "mediatek,mt8195-mfgcfg";
89        reg = <0x13fbf000 0x1000>;
90        #clock-cells = <1>;
91    };
92
93  - |
94    wpesys: clock-controller@14e00000 {
95        compatible = "mediatek,mt8195-wpesys";
96        reg = <0x14e00000 0x1000>;
97        #clock-cells = <1>;
98    };
99
100  - |
101    wpesys_vpp0: clock-controller@14e02000 {
102        compatible = "mediatek,mt8195-wpesys_vpp0";
103        reg = <0x14e02000 0x1000>;
104        #clock-cells = <1>;
105    };
106
107  - |
108    wpesys_vpp1: clock-controller@14e03000 {
109        compatible = "mediatek,mt8195-wpesys_vpp1";
110        reg = <0x14e03000 0x1000>;
111        #clock-cells = <1>;
112    };
113
114  - |
115    imgsys: clock-controller@15000000 {
116        compatible = "mediatek,mt8195-imgsys";
117        reg = <0x15000000 0x1000>;
118        #clock-cells = <1>;
119    };
120
121  - |
122    imgsys1_dip_top: clock-controller@15110000 {
123        compatible = "mediatek,mt8195-imgsys1_dip_top";
124        reg = <0x15110000 0x1000>;
125        #clock-cells = <1>;
126    };
127
128  - |
129    imgsys1_dip_nr: clock-controller@15130000 {
130        compatible = "mediatek,mt8195-imgsys1_dip_nr";
131        reg = <0x15130000 0x1000>;
132        #clock-cells = <1>;
133    };
134
135  - |
136    imgsys1_wpe: clock-controller@15220000 {
137        compatible = "mediatek,mt8195-imgsys1_wpe";
138        reg = <0x15220000 0x1000>;
139        #clock-cells = <1>;
140    };
141
142  - |
143    ipesys: clock-controller@15330000 {
144        compatible = "mediatek,mt8195-ipesys";
145        reg = <0x15330000 0x1000>;
146        #clock-cells = <1>;
147    };
148
149  - |
150    camsys: clock-controller@16000000 {
151        compatible = "mediatek,mt8195-camsys";
152        reg = <0x16000000 0x1000>;
153        #clock-cells = <1>;
154    };
155
156  - |
157    camsys_rawa: clock-controller@1604f000 {
158        compatible = "mediatek,mt8195-camsys_rawa";
159        reg = <0x1604f000 0x1000>;
160        #clock-cells = <1>;
161    };
162
163  - |
164    camsys_yuva: clock-controller@1606f000 {
165        compatible = "mediatek,mt8195-camsys_yuva";
166        reg = <0x1606f000 0x1000>;
167        #clock-cells = <1>;
168    };
169
170  - |
171    camsys_rawb: clock-controller@1608f000 {
172        compatible = "mediatek,mt8195-camsys_rawb";
173        reg = <0x1608f000 0x1000>;
174        #clock-cells = <1>;
175    };
176
177  - |
178    camsys_yuvb: clock-controller@160af000 {
179        compatible = "mediatek,mt8195-camsys_yuvb";
180        reg = <0x160af000 0x1000>;
181        #clock-cells = <1>;
182    };
183
184  - |
185    camsys_mraw: clock-controller@16140000 {
186        compatible = "mediatek,mt8195-camsys_mraw";
187        reg = <0x16140000 0x1000>;
188        #clock-cells = <1>;
189    };
190
191  - |
192    ccusys: clock-controller@17200000 {
193        compatible = "mediatek,mt8195-ccusys";
194        reg = <0x17200000 0x1000>;
195        #clock-cells = <1>;
196    };
197
198  - |
199    vdecsys_soc: clock-controller@1800f000 {
200        compatible = "mediatek,mt8195-vdecsys_soc";
201        reg = <0x1800f000 0x1000>;
202        #clock-cells = <1>;
203    };
204
205  - |
206    vdecsys: clock-controller@1802f000 {
207        compatible = "mediatek,mt8195-vdecsys";
208        reg = <0x1802f000 0x1000>;
209        #clock-cells = <1>;
210    };
211
212  - |
213    vdecsys_core1: clock-controller@1803f000 {
214        compatible = "mediatek,mt8195-vdecsys_core1";
215        reg = <0x1803f000 0x1000>;
216        #clock-cells = <1>;
217    };
218
219  - |
220    vencsys: clock-controller@1a000000 {
221        compatible = "mediatek,mt8195-vencsys";
222        reg = <0x1a000000 0x1000>;
223        #clock-cells = <1>;
224    };
225
226  - |
227    vencsys_core1: clock-controller@1b000000 {
228        compatible = "mediatek,mt8195-vencsys_core1";
229        reg = <0x1b000000 0x1000>;
230        #clock-cells = <1>;
231    };
232
233  - |
234    apusys_pll: clock-controller@190f3000 {
235        compatible = "mediatek,mt8195-apusys_pll";
236        reg = <0x190f3000 0x1000>;
237        #clock-cells = <1>;
238    };
239