xref: /linux/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml (revision 06d07429858317ded2db7986113a9e0129cd599b)
1*afd36e9dSDaniel Golle# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*afd36e9dSDaniel Golle%YAML 1.2
3*afd36e9dSDaniel Golle---
4*afd36e9dSDaniel Golle$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml#
5*afd36e9dSDaniel Golle$schema: http://devicetree.org/meta-schemas/core.yaml#
6*afd36e9dSDaniel Golle
7*afd36e9dSDaniel Golletitle: MediaTek MT7988 ethwarp Controller
8*afd36e9dSDaniel Golle
9*afd36e9dSDaniel Gollemaintainers:
10*afd36e9dSDaniel Golle  - Daniel Golle <daniel@makrotopia.org>
11*afd36e9dSDaniel Golle
12*afd36e9dSDaniel Golledescription:
13*afd36e9dSDaniel Golle  The Mediatek MT7988 ethwarp controller provides clocks and resets for the
14*afd36e9dSDaniel Golle  Ethernet related subsystems found the MT7988 SoC.
15*afd36e9dSDaniel Golle  The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
16*afd36e9dSDaniel Golle
17*afd36e9dSDaniel Golleproperties:
18*afd36e9dSDaniel Golle  compatible:
19*afd36e9dSDaniel Golle    items:
20*afd36e9dSDaniel Golle      - const: mediatek,mt7988-ethwarp
21*afd36e9dSDaniel Golle
22*afd36e9dSDaniel Golle  reg:
23*afd36e9dSDaniel Golle    maxItems: 1
24*afd36e9dSDaniel Golle
25*afd36e9dSDaniel Golle  '#clock-cells':
26*afd36e9dSDaniel Golle    const: 1
27*afd36e9dSDaniel Golle
28*afd36e9dSDaniel Golle  '#reset-cells':
29*afd36e9dSDaniel Golle    const: 1
30*afd36e9dSDaniel Golle
31*afd36e9dSDaniel Gollerequired:
32*afd36e9dSDaniel Golle  - compatible
33*afd36e9dSDaniel Golle  - reg
34*afd36e9dSDaniel Golle  - '#clock-cells'
35*afd36e9dSDaniel Golle  - '#reset-cells'
36*afd36e9dSDaniel Golle
37*afd36e9dSDaniel GolleadditionalProperties: false
38*afd36e9dSDaniel Golle
39*afd36e9dSDaniel Golleexamples:
40*afd36e9dSDaniel Golle  - |
41*afd36e9dSDaniel Golle    #include <dt-bindings/reset/ti-syscon.h>
42*afd36e9dSDaniel Golle    soc {
43*afd36e9dSDaniel Golle        #address-cells = <2>;
44*afd36e9dSDaniel Golle        #size-cells = <2>;
45*afd36e9dSDaniel Golle
46*afd36e9dSDaniel Golle        clock-controller@15031000 {
47*afd36e9dSDaniel Golle            compatible = "mediatek,mt7988-ethwarp";
48*afd36e9dSDaniel Golle            reg = <0 0x15031000 0 0x1000>;
49*afd36e9dSDaniel Golle            #clock-cells = <1>;
50*afd36e9dSDaniel Golle            #reset-cells = <1>;
51*afd36e9dSDaniel Golle        };
52*afd36e9dSDaniel Golle    };
53