xref: /linux/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5)
116a14673SYassine Oudjana# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
216a14673SYassine Oudjana%YAML 1.2
316a14673SYassine Oudjana---
432671977SRob Herring$id: http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#
532671977SRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml#
616a14673SYassine Oudjana
716a14673SYassine Oudjanatitle: MediaTek AP Mixedsys Controller
816a14673SYassine Oudjana
916a14673SYassine Oudjanamaintainers:
1016a14673SYassine Oudjana  - Michael Turquette <mturquette@baylibre.com>
1116a14673SYassine Oudjana  - Stephen Boyd <sboyd@kernel.org>
1216a14673SYassine Oudjana
1316a14673SYassine Oudjanadescription:
1416a14673SYassine Oudjana  The Mediatek apmixedsys controller provides PLLs to the system.
1516a14673SYassine Oudjana  The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
1616a14673SYassine Oudjana
1716a14673SYassine Oudjanaproperties:
1816a14673SYassine Oudjana  compatible:
1916a14673SYassine Oudjana    oneOf:
2016a14673SYassine Oudjana      - enum:
2116a14673SYassine Oudjana          - mediatek,mt6797-apmixedsys
2216a14673SYassine Oudjana          - mediatek,mt7622-apmixedsys
23cc4d9e0cSDaniel Golle          - mediatek,mt7981-apmixedsys
2416a14673SYassine Oudjana          - mediatek,mt7986-apmixedsys
25afd36e9dSDaniel Golle          - mediatek,mt7988-apmixedsys
2616a14673SYassine Oudjana          - mediatek,mt8135-apmixedsys
2716a14673SYassine Oudjana          - mediatek,mt8173-apmixedsys
2816a14673SYassine Oudjana          - mediatek,mt8516-apmixedsys
2916a14673SYassine Oudjana      - items:
3016a14673SYassine Oudjana          - const: mediatek,mt7623-apmixedsys
3116a14673SYassine Oudjana          - const: mediatek,mt2701-apmixedsys
3216a14673SYassine Oudjana          - const: syscon
3316a14673SYassine Oudjana      - items:
3416a14673SYassine Oudjana          - enum:
3516a14673SYassine Oudjana              - mediatek,mt2701-apmixedsys
3616a14673SYassine Oudjana              - mediatek,mt2712-apmixedsys
3716a14673SYassine Oudjana              - mediatek,mt6765-apmixedsys
38*5e938ef6SRob Herring (Arm)              - mediatek,mt6779-apmixed
39d5099c95SAngeloGioacchino Del Regno              - mediatek,mt6795-apmixedsys
4016a14673SYassine Oudjana              - mediatek,mt7629-apmixedsys
4116a14673SYassine Oudjana              - mediatek,mt8167-apmixedsys
4216a14673SYassine Oudjana              - mediatek,mt8183-apmixedsys
4316a14673SYassine Oudjana          - const: syscon
4416a14673SYassine Oudjana
4516a14673SYassine Oudjana  reg:
4616a14673SYassine Oudjana    maxItems: 1
4716a14673SYassine Oudjana
4816a14673SYassine Oudjana  '#clock-cells':
4916a14673SYassine Oudjana    const: 1
5016a14673SYassine Oudjana
5116a14673SYassine Oudjanarequired:
5216a14673SYassine Oudjana  - compatible
5316a14673SYassine Oudjana  - reg
5416a14673SYassine Oudjana  - '#clock-cells'
5516a14673SYassine Oudjana
5616a14673SYassine OudjanaadditionalProperties: false
5716a14673SYassine Oudjana
5816a14673SYassine Oudjanaexamples:
5916a14673SYassine Oudjana  - |
6016a14673SYassine Oudjana    apmixedsys: clock-controller@10209000 {
6116a14673SYassine Oudjana        compatible = "mediatek,mt8173-apmixedsys";
6216a14673SYassine Oudjana        reg = <0x10209000 0x1000>;
6316a14673SYassine Oudjana        #clock-cells = <1>;
6416a14673SYassine Oudjana    };
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