1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/marvell,mvebu-core-clock.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Marvell MVEBU SoC core clock 8 9maintainers: 10 - Andrew Lunn <andrew@lunn.ch> 11 - Gregory Clement <gregory.clement@bootlin.com> 12 13description: > 14 Marvell MVEBU SoCs usually allow to determine core clock frequencies by 15 reading the Sample-At-Reset (SAR) register. The core clock consumer should 16 specify the desired clock by having the clock ID in its "clocks" phandle cell. 17 18 The following is a list of provided IDs and clock names on Armada 370/XP: 19 0 = tclk (Internal Bus clock) 20 1 = cpuclk (CPU clock) 21 2 = nbclk (L2 Cache clock) 22 3 = hclk (DRAM control clock) 23 4 = dramclk (DDR clock) 24 25 The following is a list of provided IDs and clock names on Armada 375: 26 0 = tclk (Internal Bus clock) 27 1 = cpuclk (CPU clock) 28 2 = l2clk (L2 Cache clock) 29 3 = ddrclk (DDR clock) 30 31 The following is a list of provided IDs and clock names on Armada 380/385: 32 0 = tclk (Internal Bus clock) 33 1 = cpuclk (CPU clock) 34 2 = l2clk (L2 Cache clock) 35 3 = ddrclk (DDR clock) 36 37 The following is a list of provided IDs and clock names on Armada 39x: 38 0 = tclk (Internal Bus clock) 39 1 = cpuclk (CPU clock) 40 2 = nbclk (Coherent Fabric clock) 41 3 = hclk (SDRAM Controller Internal Clock) 42 4 = dclk (SDRAM Interface Clock) 43 5 = refclk (Reference Clock) 44 45 The following is a list of provided IDs and clock names on 98dx3236: 46 0 = tclk (Internal Bus clock) 47 1 = cpuclk (CPU clock) 48 2 = ddrclk (DDR clock) 49 3 = mpll (MPLL Clock) 50 51 The following is a list of provided IDs and clock names on Kirkwood and Dove: 52 0 = tclk (Internal Bus clock) 53 1 = cpuclk (CPU0 clock) 54 2 = l2clk (L2 Cache clock derived from CPU0 clock) 55 3 = ddrclk (DDR controller clock derived from CPU0 clock) 56 57 The following is a list of provided IDs and clock names on Orion5x: 58 0 = tclk (Internal Bus clock) 59 1 = cpuclk (CPU0 clock) 60 2 = ddrclk (DDR controller clock derived from CPU0 clock) 61 62properties: 63 compatible: 64 enum: 65 - marvell,armada-370-core-clock 66 - marvell,armada-375-core-clock 67 - marvell,armada-380-core-clock 68 - marvell,armada-390-core-clock 69 - marvell,armada-xp-core-clock 70 - marvell,dove-core-clock 71 - marvell,kirkwood-core-clock 72 - marvell,mv88f5181-core-clock 73 - marvell,mv88f5182-core-clock 74 - marvell,mv88f5281-core-clock 75 - marvell,mv88f6180-core-clock 76 - marvell,mv88f6183-core-clock 77 - marvell,mv98dx1135-core-clock 78 - marvell,mv98dx3236-core-clock 79 80 reg: 81 maxItems: 1 82 83 '#clock-cells': 84 const: 1 85 86 clock-output-names: 87 description: Overwrite default clock output names. 88 89required: 90 - compatible 91 - reg 92 - '#clock-cells' 93 94additionalProperties: false 95