xref: /linux/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: IDT VersaClock 5 and 6 programmable I2C clock generators
8
9description: |
10  The IDT VersaClock 5 and VersaClock 6 are programmable I2C
11  clock generators providing from 3 to 12 output clocks.
12
13  When referencing the provided clock in the DT using phandle and clock
14  specifier, the following mapping applies:
15
16  - 5P49V5923:
17    0 -- OUT0_SEL_I2CB
18    1 -- OUT1
19    2 -- OUT2
20
21  - 5P49V5933:
22    0 -- OUT0_SEL_I2CB
23    1 -- OUT1
24    2 -- OUT4
25
26  - other parts:
27    0 -- OUT0_SEL_I2CB
28    1 -- OUT1
29    2 -- OUT2
30    3 -- OUT3
31    4 -- OUT4
32
33  The idt,shutdown and idt,output-enable-active properties control the
34  SH (en_global_shutdown) and SP bits of the Primary Source and Shutdown
35  Register, respectively. Their behavior is summarized by the following
36  table:
37
38  SH SP Output when the SD/OE pin is Low/High
39  == == =====================================
40   0  0 Active/Inactive
41   0  1 Inactive/Active
42   1  0 Active/Shutdown
43   1  1 Inactive/Shutdown
44
45  The case where SH and SP are both 1 is likely not very interesting.
46
47maintainers:
48  - Luca Ceresoli <luca.ceresoli@bootlin.com>
49
50properties:
51  compatible:
52    enum:
53      - idt,5p49v5923
54      - idt,5p49v5925
55      - idt,5p49v5933
56      - idt,5p49v5935
57      - idt,5p49v60
58      - idt,5p49v6901
59      - idt,5p49v6965
60      - idt,5p49v6975
61
62  reg:
63    description: I2C device address
64    enum: [ 0x68, 0x6a ]
65
66  '#clock-cells':
67    const: 1
68
69  clock-names:
70    minItems: 1
71    maxItems: 2
72    items:
73      enum: [ xin, clkin ]
74  clocks:
75    minItems: 1
76    maxItems: 2
77
78  idt,xtal-load-femtofarads:
79    minimum: 9000
80    maximum: 22760
81    description: Optional load capacitor for XTAL1 and XTAL2
82
83  idt,shutdown:
84    $ref: /schemas/types.yaml#/definitions/uint32
85    enum: [0, 1]
86    description: |
87      If 1, this enables the shutdown functionality: the chip will be
88      shut down if the SD/OE pin is driven high. If 0, this disables the
89      shutdown functionality: the chip will never be shut down based on
90      the value of the SD/OE pin. This property corresponds to the SH
91      bit of the Primary Source and Shutdown Register.
92
93  idt,output-enable-active:
94    $ref: /schemas/types.yaml#/definitions/uint32
95    enum: [0, 1]
96    description: |
97      If 1, this enables output when the SD/OE pin is high, and disables
98      output when the SD/OE pin is low. If 0, this disables output when
99      the SD/OE pin is high, and enables output when the SD/OE pin is
100      low. This corresponds to the SP bit of the Primary Source and
101      Shutdown Register.
102
103patternProperties:
104  "^OUT[1-4]$":
105    type: object
106    description:
107      Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
108      Configuration" in the Versaclock 5/6/6E Family Register Description
109      and Programming Guide.
110    properties:
111      idt,mode:
112        description:
113          The output drive mode. Values defined in dt-bindings/clock/versaclock.h
114        $ref: /schemas/types.yaml#/definitions/uint32
115        minimum: 0
116        maximum: 6
117      idt,voltage-microvolt:
118        description: The output drive voltage.
119        enum: [ 1800000, 2500000, 3300000 ]
120      idt,slew-percent:
121        description: The Slew rate control for CMOS single-ended.
122        enum: [ 80, 85, 90, 100 ]
123    additionalProperties: false
124
125required:
126  - compatible
127  - reg
128  - '#clock-cells'
129
130allOf:
131  - if:
132      properties:
133        compatible:
134          enum:
135            - idt,5p49v5933
136            - idt,5p49v5935
137            - idt,5p49v6975
138    then:
139      # Devices with builtin crystal + optional external input
140      properties:
141        clock-names:
142          const: clkin
143        clocks:
144          maxItems: 1
145    else:
146      # Devices without builtin crystal
147      required:
148        - clock-names
149        - clocks
150
151additionalProperties: false
152
153examples:
154  - |
155    #include <dt-bindings/clock/versaclock.h>
156
157    /* 25MHz reference crystal */
158    ref25: ref25m {
159        compatible = "fixed-clock";
160        #clock-cells = <0>;
161        clock-frequency = <25000000>;
162    };
163
164    i2c@0 {
165        reg = <0x0 0x100>;
166        #address-cells = <1>;
167        #size-cells = <0>;
168
169        /* IDT 5P49V5923 I2C clock generator */
170        vc5: clock-generator@6a {
171            compatible = "idt,5p49v5923";
172            reg = <0x6a>;
173            #clock-cells = <1>;
174
175            /* Connect XIN input to 25MHz reference */
176            clocks = <&ref25m>;
177            clock-names = "xin";
178
179            /* Set the SD/OE pin's settings */
180            idt,shutdown = <0>;
181            idt,output-enable-active = <0>;
182
183            OUT1 {
184                idt,mode = <VC5_CMOSD>;
185                idt,voltage-microvolt = <1800000>;
186                idt,slew-percent = <80>;
187            };
188
189            OUT4 {
190                idt,mode = <VC5_LVDS>;
191            };
192        };
193    };
194
195...
196