xref: /linux/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml (revision 9d69d47fd399137d41b744065aab2f9677ccc377)
145c94018SLuca Ceresoli# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
245c94018SLuca Ceresoli%YAML 1.2
345c94018SLuca Ceresoli---
445c94018SLuca Ceresoli$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
545c94018SLuca Ceresoli$schema: http://devicetree.org/meta-schemas/core.yaml#
645c94018SLuca Ceresoli
7*9d69d47fSKrzysztof Kozlowskititle: IDT VersaClock 5 and 6 programmable I2C clock generators
845c94018SLuca Ceresoli
945c94018SLuca Ceresolidescription: |
1045c94018SLuca Ceresoli  The IDT VersaClock 5 and VersaClock 6 are programmable I2C
1145c94018SLuca Ceresoli  clock generators providing from 3 to 12 output clocks.
1245c94018SLuca Ceresoli
1345c94018SLuca Ceresoli  When referencing the provided clock in the DT using phandle and clock
1445c94018SLuca Ceresoli  specifier, the following mapping applies:
1545c94018SLuca Ceresoli
1645c94018SLuca Ceresoli  - 5P49V5923:
1745c94018SLuca Ceresoli    0 -- OUT0_SEL_I2CB
1845c94018SLuca Ceresoli    1 -- OUT1
1945c94018SLuca Ceresoli    2 -- OUT2
2045c94018SLuca Ceresoli
2145c94018SLuca Ceresoli  - 5P49V5933:
2245c94018SLuca Ceresoli    0 -- OUT0_SEL_I2CB
2345c94018SLuca Ceresoli    1 -- OUT1
2445c94018SLuca Ceresoli    2 -- OUT4
2545c94018SLuca Ceresoli
2645c94018SLuca Ceresoli  - other parts:
2745c94018SLuca Ceresoli    0 -- OUT0_SEL_I2CB
2845c94018SLuca Ceresoli    1 -- OUT1
2945c94018SLuca Ceresoli    2 -- OUT2
3045c94018SLuca Ceresoli    3 -- OUT3
3145c94018SLuca Ceresoli    4 -- OUT4
3245c94018SLuca Ceresoli
33275e4e2dSSean Anderson  The idt,shutdown and idt,output-enable-active properties control the
34275e4e2dSSean Anderson  SH (en_global_shutdown) and SP bits of the Primary Source and Shutdown
35275e4e2dSSean Anderson  Register, respectively. Their behavior is summarized by the following
36275e4e2dSSean Anderson  table:
37275e4e2dSSean Anderson
38275e4e2dSSean Anderson  SH SP Output when the SD/OE pin is Low/High
39275e4e2dSSean Anderson  == == =====================================
40275e4e2dSSean Anderson   0  0 Active/Inactive
41275e4e2dSSean Anderson   0  1 Inactive/Active
42275e4e2dSSean Anderson   1  0 Active/Shutdown
43275e4e2dSSean Anderson   1  1 Inactive/Shutdown
44275e4e2dSSean Anderson
45275e4e2dSSean Anderson  The case where SH and SP are both 1 is likely not very interesting.
46275e4e2dSSean Anderson
4745c94018SLuca Ceresolimaintainers:
48216d1a80SLuca Ceresoli  - Luca Ceresoli <luca.ceresoli@bootlin.com>
4945c94018SLuca Ceresoli
5045c94018SLuca Ceresoliproperties:
5145c94018SLuca Ceresoli  compatible:
5245c94018SLuca Ceresoli    enum:
5345c94018SLuca Ceresoli      - idt,5p49v5923
5445c94018SLuca Ceresoli      - idt,5p49v5925
5545c94018SLuca Ceresoli      - idt,5p49v5933
5645c94018SLuca Ceresoli      - idt,5p49v5935
5745c94018SLuca Ceresoli      - idt,5p49v6901
5845c94018SLuca Ceresoli      - idt,5p49v6965
59f0fa3a36SMatthias Fend      - idt,5p49v6975
6045c94018SLuca Ceresoli
6145c94018SLuca Ceresoli  reg:
6245c94018SLuca Ceresoli    description: I2C device address
6345c94018SLuca Ceresoli    enum: [ 0x68, 0x6a ]
6445c94018SLuca Ceresoli
6545c94018SLuca Ceresoli  '#clock-cells':
6645c94018SLuca Ceresoli    const: 1
6745c94018SLuca Ceresoli
685be478f9SRob Herring  clock-names:
695be478f9SRob Herring    minItems: 1
705be478f9SRob Herring    maxItems: 2
715be478f9SRob Herring    items:
725be478f9SRob Herring      enum: [ xin, clkin ]
735be478f9SRob Herring  clocks:
745be478f9SRob Herring    minItems: 1
755be478f9SRob Herring    maxItems: 2
765be478f9SRob Herring
7731e7aa7eSAdam Ford  idt,xtal-load-femtofarads:
7831e7aa7eSAdam Ford    minimum: 9000
7931e7aa7eSAdam Ford    maximum: 22760
8031e7aa7eSAdam Ford    description: Optional load capacitor for XTAL1 and XTAL2
8131e7aa7eSAdam Ford
82275e4e2dSSean Anderson  idt,shutdown:
83275e4e2dSSean Anderson    $ref: /schemas/types.yaml#/definitions/uint32
84275e4e2dSSean Anderson    enum: [0, 1]
85275e4e2dSSean Anderson    description: |
86275e4e2dSSean Anderson      If 1, this enables the shutdown functionality: the chip will be
87275e4e2dSSean Anderson      shut down if the SD/OE pin is driven high. If 0, this disables the
88275e4e2dSSean Anderson      shutdown functionality: the chip will never be shut down based on
89275e4e2dSSean Anderson      the value of the SD/OE pin. This property corresponds to the SH
90275e4e2dSSean Anderson      bit of the Primary Source and Shutdown Register.
91275e4e2dSSean Anderson
92275e4e2dSSean Anderson  idt,output-enable-active:
93275e4e2dSSean Anderson    $ref: /schemas/types.yaml#/definitions/uint32
94275e4e2dSSean Anderson    enum: [0, 1]
95275e4e2dSSean Anderson    description: |
96275e4e2dSSean Anderson      If 1, this enables output when the SD/OE pin is high, and disables
97275e4e2dSSean Anderson      output when the SD/OE pin is low. If 0, this disables output when
98275e4e2dSSean Anderson      the SD/OE pin is high, and enables output when the SD/OE pin is
99275e4e2dSSean Anderson      low. This corresponds to the SP bit of the Primary Source and
100275e4e2dSSean Anderson      Shutdown Register.
101275e4e2dSSean Anderson
10245c94018SLuca CeresolipatternProperties:
10345c94018SLuca Ceresoli  "^OUT[1-4]$":
10445c94018SLuca Ceresoli    type: object
10545c94018SLuca Ceresoli    description:
10645c94018SLuca Ceresoli      Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
10745c94018SLuca Ceresoli      Configuration" in the Versaclock 5/6/6E Family Register Description
10845c94018SLuca Ceresoli      and Programming Guide.
10945c94018SLuca Ceresoli    properties:
11045c94018SLuca Ceresoli      idt,mode:
11145c94018SLuca Ceresoli        description:
112ba6165bcSLukas Bulwahn          The output drive mode. Values defined in dt-bindings/clock/versaclock.h
11345c94018SLuca Ceresoli        $ref: /schemas/types.yaml#/definitions/uint32
11445c94018SLuca Ceresoli        minimum: 0
11545c94018SLuca Ceresoli        maximum: 6
11645c94018SLuca Ceresoli      idt,voltage-microvolt:
11745c94018SLuca Ceresoli        description: The output drive voltage.
11845c94018SLuca Ceresoli        enum: [ 1800000, 2500000, 3300000 ]
11945c94018SLuca Ceresoli      idt,slew-percent:
12045c94018SLuca Ceresoli        description: The Slew rate control for CMOS single-ended.
12145c94018SLuca Ceresoli        enum: [ 80, 85, 90, 100 ]
12289f8a707SSean Anderson    additionalProperties: false
12345c94018SLuca Ceresoli
12445c94018SLuca Ceresolirequired:
12545c94018SLuca Ceresoli  - compatible
12645c94018SLuca Ceresoli  - reg
12745c94018SLuca Ceresoli  - '#clock-cells'
128275e4e2dSSean Anderson  - idt,shutdown
129275e4e2dSSean Anderson  - idt,output-enable-active
13045c94018SLuca Ceresoli
13145c94018SLuca CeresoliallOf:
13245c94018SLuca Ceresoli  - if:
13345c94018SLuca Ceresoli      properties:
13445c94018SLuca Ceresoli        compatible:
13545c94018SLuca Ceresoli          enum:
13645c94018SLuca Ceresoli            - idt,5p49v5933
13745c94018SLuca Ceresoli            - idt,5p49v5935
138f0fa3a36SMatthias Fend            - idt,5p49v6975
13945c94018SLuca Ceresoli    then:
14045c94018SLuca Ceresoli      # Devices with builtin crystal + optional external input
14145c94018SLuca Ceresoli      properties:
14245c94018SLuca Ceresoli        clock-names:
14345c94018SLuca Ceresoli          const: clkin
14445c94018SLuca Ceresoli        clocks:
14545c94018SLuca Ceresoli          maxItems: 1
14645c94018SLuca Ceresoli    else:
14745c94018SLuca Ceresoli      # Devices without builtin crystal
14845c94018SLuca Ceresoli      required:
14945c94018SLuca Ceresoli        - clock-names
15045c94018SLuca Ceresoli        - clocks
15145c94018SLuca Ceresoli
1525be478f9SRob HerringadditionalProperties: false
1535be478f9SRob Herring
15445c94018SLuca Ceresoliexamples:
15545c94018SLuca Ceresoli  - |
156ba6165bcSLukas Bulwahn    #include <dt-bindings/clock/versaclock.h>
15745c94018SLuca Ceresoli
15845c94018SLuca Ceresoli    /* 25MHz reference crystal */
15945c94018SLuca Ceresoli    ref25: ref25m {
16045c94018SLuca Ceresoli        compatible = "fixed-clock";
16145c94018SLuca Ceresoli        #clock-cells = <0>;
16245c94018SLuca Ceresoli        clock-frequency = <25000000>;
16345c94018SLuca Ceresoli    };
16445c94018SLuca Ceresoli
16545c94018SLuca Ceresoli    i2c@0 {
16645c94018SLuca Ceresoli        reg = <0x0 0x100>;
16745c94018SLuca Ceresoli        #address-cells = <1>;
16845c94018SLuca Ceresoli        #size-cells = <0>;
16945c94018SLuca Ceresoli
17045c94018SLuca Ceresoli        /* IDT 5P49V5923 I2C clock generator */
17145c94018SLuca Ceresoli        vc5: clock-generator@6a {
17245c94018SLuca Ceresoli            compatible = "idt,5p49v5923";
17345c94018SLuca Ceresoli            reg = <0x6a>;
17445c94018SLuca Ceresoli            #clock-cells = <1>;
17545c94018SLuca Ceresoli
17645c94018SLuca Ceresoli            /* Connect XIN input to 25MHz reference */
17745c94018SLuca Ceresoli            clocks = <&ref25m>;
17845c94018SLuca Ceresoli            clock-names = "xin";
17945c94018SLuca Ceresoli
180275e4e2dSSean Anderson            /* Set the SD/OE pin's settings */
181275e4e2dSSean Anderson            idt,shutdown = <0>;
182275e4e2dSSean Anderson            idt,output-enable-active = <0>;
183275e4e2dSSean Anderson
18445c94018SLuca Ceresoli            OUT1 {
18589f8a707SSean Anderson                idt,mode = <VC5_CMOSD>;
18689f8a707SSean Anderson                idt,voltage-microvolt = <1800000>;
18745c94018SLuca Ceresoli                idt,slew-percent = <80>;
18845c94018SLuca Ceresoli            };
18945c94018SLuca Ceresoli
19045c94018SLuca Ceresoli            OUT4 {
19189f8a707SSean Anderson                idt,mode = <VC5_LVDS>;
19245c94018SLuca Ceresoli            };
19345c94018SLuca Ceresoli        };
19445c94018SLuca Ceresoli    };
19545c94018SLuca Ceresoli
19645c94018SLuca Ceresoli...
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