1*3b6b13edSManivannan Sadhasivam* Hisilicon Hi3670 Clock Controller 2*3b6b13edSManivannan Sadhasivam 3*3b6b13edSManivannan SadhasivamThe Hi3670 clock controller generates and supplies clock to various 4*3b6b13edSManivannan Sadhasivamcontrollers within the Hi3670 SoC. 5*3b6b13edSManivannan Sadhasivam 6*3b6b13edSManivannan SadhasivamRequired Properties: 7*3b6b13edSManivannan Sadhasivam 8*3b6b13edSManivannan Sadhasivam- compatible: the compatible should be one of the following strings to 9*3b6b13edSManivannan Sadhasivam indicate the clock controller functionality. 10*3b6b13edSManivannan Sadhasivam 11*3b6b13edSManivannan Sadhasivam - "hisilicon,hi3670-crgctrl" 12*3b6b13edSManivannan Sadhasivam - "hisilicon,hi3670-pctrl" 13*3b6b13edSManivannan Sadhasivam - "hisilicon,hi3670-pmuctrl" 14*3b6b13edSManivannan Sadhasivam - "hisilicon,hi3670-sctrl" 15*3b6b13edSManivannan Sadhasivam - "hisilicon,hi3670-iomcu" 16*3b6b13edSManivannan Sadhasivam - "hisilicon,hi3670-media1-crg" 17*3b6b13edSManivannan Sadhasivam - "hisilicon,hi3670-media2-crg" 18*3b6b13edSManivannan Sadhasivam 19*3b6b13edSManivannan Sadhasivam- reg: physical base address of the controller and length of memory mapped 20*3b6b13edSManivannan Sadhasivam region. 21*3b6b13edSManivannan Sadhasivam 22*3b6b13edSManivannan Sadhasivam- #clock-cells: should be 1. 23*3b6b13edSManivannan Sadhasivam 24*3b6b13edSManivannan SadhasivamEach clock is assigned an identifier and client nodes use this identifier 25*3b6b13edSManivannan Sadhasivamto specify the clock which they consume. 26*3b6b13edSManivannan Sadhasivam 27*3b6b13edSManivannan SadhasivamAll these identifier could be found in <dt-bindings/clock/hi3670-clock.h>. 28*3b6b13edSManivannan Sadhasivam 29*3b6b13edSManivannan SadhasivamExamples: 30*3b6b13edSManivannan Sadhasivam crg_ctrl: clock-controller@fff35000 { 31*3b6b13edSManivannan Sadhasivam compatible = "hisilicon,hi3670-crgctrl", "syscon"; 32*3b6b13edSManivannan Sadhasivam reg = <0x0 0xfff35000 0x0 0x1000>; 33*3b6b13edSManivannan Sadhasivam #clock-cells = <1>; 34*3b6b13edSManivannan Sadhasivam }; 35*3b6b13edSManivannan Sadhasivam 36*3b6b13edSManivannan Sadhasivam uart0: serial@fdf02000 { 37*3b6b13edSManivannan Sadhasivam compatible = "arm,pl011", "arm,primecell"; 38*3b6b13edSManivannan Sadhasivam reg = <0x0 0xfdf02000 0x0 0x1000>; 39*3b6b13edSManivannan Sadhasivam interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 40*3b6b13edSManivannan Sadhasivam clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>, 41*3b6b13edSManivannan Sadhasivam <&crg_ctrl HI3670_PCLK>; 42*3b6b13edSManivannan Sadhasivam clock-names = "uartclk", "apb_pclk"; 43*3b6b13edSManivannan Sadhasivam }; 44