1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Google GS101 SoC clock controller 8 9maintainers: 10 - Peter Griffin <peter.griffin@linaro.org> 11 12description: | 13 Google GS101 clock controller is comprised of several CMU units, generating 14 clocks for different domains. Those CMU units are modeled as separate device 15 tree nodes, and might depend on each other. The root clock in that clock tree 16 is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate 17 clock in dts. 18 19 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and 20 dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. 21 22 Each clock is assigned an identifier and client nodes can use this identifier 23 to specify the clock which they consume. All clocks available for usage 24 in clock consumer nodes are defined as preprocessor macros in 25 'dt-bindings/clock/gs101.h' header. 26 27properties: 28 compatible: 29 enum: 30 - google,gs101-cmu-top 31 - google,gs101-cmu-apm 32 - google,gs101-cmu-misc 33 - google,gs101-cmu-hsi0 34 - google,gs101-cmu-hsi2 35 - google,gs101-cmu-peric0 36 - google,gs101-cmu-peric1 37 38 clocks: 39 minItems: 1 40 maxItems: 5 41 42 clock-names: 43 minItems: 1 44 maxItems: 5 45 46 "#clock-cells": 47 const: 1 48 49 reg: 50 maxItems: 1 51 52required: 53 - compatible 54 - "#clock-cells" 55 - clocks 56 - clock-names 57 - reg 58 59allOf: 60 - if: 61 properties: 62 compatible: 63 contains: 64 enum: 65 - google,gs101-cmu-top 66 - google,gs101-cmu-apm 67 then: 68 properties: 69 clocks: 70 items: 71 - description: External reference clock (24.576 MHz) 72 73 clock-names: 74 items: 75 - const: oscclk 76 77 - if: 78 properties: 79 compatible: 80 contains: 81 const: google,gs101-cmu-hsi0 82 83 then: 84 properties: 85 clocks: 86 items: 87 - description: External reference clock (24.576 MHz) 88 - description: HSI0 bus clock (from CMU_TOP) 89 - description: DPGTC (from CMU_TOP) 90 - description: USB DRD controller clock (from CMU_TOP) 91 - description: USB Display Port debug clock (from CMU_TOP) 92 93 clock-names: 94 items: 95 - const: oscclk 96 - const: bus 97 - const: dpgtc 98 - const: usb31drd 99 - const: usbdpdbg 100 101 - if: 102 properties: 103 compatible: 104 contains: 105 enum: 106 - google,gs101-cmu-hsi2 107 108 then: 109 properties: 110 clocks: 111 items: 112 - description: External reference clock (24.576 MHz) 113 - description: High Speed Interface bus clock (from CMU_TOP) 114 - description: High Speed Interface pcie clock (from CMU_TOP) 115 - description: High Speed Interface ufs clock (from CMU_TOP) 116 - description: High Speed Interface mmc clock (from CMU_TOP) 117 118 clock-names: 119 items: 120 - const: oscclk 121 - const: bus 122 - const: pcie 123 - const: ufs 124 - const: mmc 125 126 - if: 127 properties: 128 compatible: 129 contains: 130 const: google,gs101-cmu-misc 131 132 then: 133 properties: 134 clocks: 135 items: 136 - description: Misc bus clock (from CMU_TOP) 137 - description: Misc sss clock (from CMU_TOP) 138 139 clock-names: 140 items: 141 - const: bus 142 - const: sss 143 144 - if: 145 properties: 146 compatible: 147 contains: 148 enum: 149 - google,gs101-cmu-peric0 150 - google,gs101-cmu-peric1 151 152 then: 153 properties: 154 clocks: 155 items: 156 - description: External reference clock (24.576 MHz) 157 - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP) 158 - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP) 159 160 clock-names: 161 items: 162 - const: oscclk 163 - const: bus 164 - const: ip 165 166additionalProperties: false 167 168examples: 169 # Clock controller node for CMU_TOP 170 - | 171 #include <dt-bindings/clock/google,gs101.h> 172 173 cmu_top: clock-controller@1e080000 { 174 compatible = "google,gs101-cmu-top"; 175 reg = <0x1e080000 0x8000>; 176 #clock-cells = <1>; 177 clocks = <&ext_24_5m>; 178 clock-names = "oscclk"; 179 }; 180 181... 182